UCAgent: An End-to-End Agent for Block-Level Functional Verification

2026-03-26

AI Summary

This work addresses the challenges of high complexity and prolonged cycles in functional verification for modern chip design, where conventional approaches struggle with automatically generating reliable testbenches, orchestrating multi-step workflows, and ensuring consistency. The paper proposes UCAgent, an end-to-end LLM-driven agent that innovatively employs a pure Python verification framework—eliminating the need for SystemVerilog code generation—a 31-stage fine-grained configurable workflow, and a Verification Consistency Labeling Mechanism (VCLM) to fully automate module-level functional verification. Experimental results on modules such as UART, FPU, and integer dividers demonstrate up to 98.5% code coverage and 100% functional coverage, along with the successful detection of previously unknown bugs in real designs, significantly enhancing verification reliability and traceability.

Abstract

Functional verification remains a critical bottleneck in modern IC development cycles, accounting for approximately 70% of total development time in many projects. However, traditional methods, including constrained-random and formal verification, struggle to keep pace with the growing complexity of modern semiconductor designs. While recent advances in Large Language Models (LLMs) have shown promise in code generation and task automation, significant challenges hinder the realization of end-to-end functional verification automation. These challenges include (i) limited accuracy in generating Verilog/SystemVerilog verification code, (ii) the fragility of LLMs when executing complex, multi-step verification workflows, and (iii) the difficulty of maintaining verification consistency across specifications, coverage models, and test cases throughout the workflow. To address these challenges, we propose UCAgent, an end-to-end agent that automates hardware block-level functional verification based on three core mechanisms. First, we establish a pure Python verification environment using Picker and Toffee to avoid relying on LLM-generated SystemVerilog verification code. Second, we introduce a configurable 31-stage fine-grained verification workflow to guide the LLM, where each stage is verified by an automated checker. Furthermore, we propose a Verification Consistency Labeling Mechanism (VCLM) that assigns hierarchical labels to LLM-generated artifacts, improving the reliability and traceability of verification. Experimental results show that UCAgent can complete end-to-end automated verification on multiple modules, including the UART, FPU, and integer divider modules, achieving up to 98.5% code coverage and up to 100% functional coverage. UCAgent also discovers previously unidentified design defects in realistic designs, demonstrating its practical potential.

Problem

• functional verification
• Large Language Models
• verification consistency
• SystemVerilog
• IC development

Innovation

• UCAgent
• end-to-end verification
• LLM-based verification
• Verification Consistency Labeling Mechanism
• Python-based verification environment