Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI

2025-09-29

AI Summary

This study systematically evaluates the security of three on-chip interconnect buses—Wishbone, AXI-Lite, and AXI—under fault injection attacks, revealing significant differences in their vulnerability during IP-core communication. To address the lack of holistic fault resilience assessment, we propose the first quantitative evaluation model integrating spatial vulnerability distribution with temporal dependencies. Our approach employs transaction-level simulation-driven fault injection, coupled with statistical analysis to characterize failure propagation paths and timing sensitivity under multi-fault scenarios. Experimental results demonstrate that AXI exhibits substantially higher fault tolerance and lower attack success rates compared to Wishbone and AXI-Lite. While all three protocols harbor exploitable security vulnerabilities, their fault propagation mechanisms and defensive time windows differ markedly. These findings provide empirical evidence and theoretical foundations for interconnect architecture selection and attack-resilient design in safety-critical SoCs.

Technology Category

• Philosophy and Ethics of AI: Safety, Robustness & Trustworthiness
• Natural Language Processing: Safety and Robustness
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems

Application Category

• Security and Privacy: Large-scale security measurements
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• User Modeling, Personalization and Recommendation: Attacks and countermeasures in recommendation systems

Abstract

Fault injection attacks exploit physical disturbances to compromise the functionality and security of integrated circuits. As System on Chip (SoC) architectures grow in complexity, the vulnerability of on chip communication fabrics has become increasingly prominent. Buses, serving as interconnects among various IP cores, represent potential vectors for fault-based exploitation. In this study, we perform simulation-driven fault injection across three mainstream bus protocols Wishbone, AXI Lite, and AXI. We systematically examine fault success rates, spatial vulnerability distributions, and timing dependencies to characterize how faults interact with bus-level transactions. The results uncover consistent behavioral patterns across protocols, offering practical insights for both attack modeling and the development of resilient SoC designs.

Problem

• Evaluating fault injection vulnerabilities in on-chip interconnects
• Comparing fault success rates across Wishbone, AXI-Lite, and AXI protocols
• Analyzing spatial and temporal dependencies in bus-level fault interactions

Innovation

• Simulation-driven fault injection across three bus protocols
• Systematically examined fault success rates and vulnerabilities
• Uncovered consistent behavioral patterns for resilient SoC designs