Pedagogically Motivated and Composable Open-Source RISC-V Processors for Computer Science Education

2025-09-24

AI Summary

To address the lack of open-source, user-friendly, and robust RISC-V implementations suitable for computer systems education and hobbyist use, this paper proposes the first RISC-V processor evaluation framework explicitly designed for teaching. We develop a modular, component-decoupled hardware architecture—implemented in Chisel and synthesizable Verilog—that supports on-demand configuration and enables scalable, easy integration into pedagogical environments. Our contributions are threefold: (1) a teaching-oriented design standard and evaluation framework emphasizing pedagogical adaptability; (2) open-sourcing of a complete toolchain, synthesizable processor core, and accompanying educational materials; and (3) empirical validation in undergraduate courses, demonstrating significant improvements in students’ conceptual understanding of instruction sets, pipelining, and hardware abstraction, as well as increased hands-on engagement. The implementation is publicly available on GitHub, supporting both classroom instruction and self-directed learning in computer architecture.

Technology Category

• Computer Vision: Learning & Optimization for CV
• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: (Computational) Cognitive Architectures

Application Category

• Responsible Web: Data and user privacy-enhancing technologies for the Web
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Systems and Infrastructure for Web, Mobile and WoT: Experiences and lessons learnt from Web-based algorithms and system deployments

Abstract

While most instruction set architectures (ISAs) are only available to use through the purchase of a restrictive commercial license, the RISC-V ISA presents a free and open-source alternative. Due to this availability, many free and open-source implementations have been developed and can be accessed on platforms such as GitHub. If an open source, easy-to-use, and robust RISC-V implementation could be obtained, it could be easily adapted for pedagogical and amateur use. In this work we accomplish three goals in relation to this outlook. First, we propose a set of criteria for evaluating the components of a RISC-V implementation's ecosystem from a pedagogical perspective. Second, we analyze a number of existing open-source RISC-V implementations to determine how many of the criteria they fulfill. We then develop a comprehensive solution that meets all of these criterion and is released open-source for other instructors to use. The framework is developed in a composable way that it's different components can be disaggregated per individual course needs. Finally, we also report on a limited study of student feedback.

Problem

• Developing open-source RISC-V processors for computer science education
• Creating composable processors adaptable to different course requirements
• Establishing pedagogical criteria for evaluating RISC-V educational tools

Innovation

• Open-source RISC-V processors for education
• Composable framework for customizable course needs
• Pedagogical criteria to evaluate existing implementations