Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI

2024-11-21

arXiv.org

AI Summary

To address the low efficiency and poor scalability of manual SPICE netlist generation in analog circuit design automation, this paper proposes the first end-to-end large language model (LLM)-driven framework for generating executable SPICE netlists directly from schematic images. Methodologically, we introduce a novel three-stage collaborative pipeline—circuit annotation, prompt tuning, and netlist verification—integrating multimodal LLMs (e.g., GPT-4), circuit semantic modeling, structured prompt engineering, and SPICE syntax-constrained validation. Our contributions include: (1) releasing the first large-scale, publicly available analog schematic–netlist paired dataset; (2) achieving high-accuracy, generalizable netlist generation—outperforming all baselines significantly on a benchmark of 2,100 schematics spanning diverse complexity levels; and (3) establishing critical infrastructure to support efficient fine-tuning and rigorous validation of domain-specific LLMs for analog circuit design.

Technology Category

• Machine Learning: Large Multimodal Models (LMMs)
• Computer Vision: Large Vision Models
• Natural Language Processing: (Large) Language Models

Application Category

• Economics, Online Markets and Human Computation: Humans versus LLMs for data annotation and labeling
• User Modeling, Personalization and Recommendation: Large Language Models (LLM) for user modeling and recommendation
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs

Abstract

Masala-CHAI is the first fully automated framework leveraging large language models (LLMs) to generate Simulation Programs with Integrated Circuit Emphasis (SPICE) netlists. It addresses a long-standing challenge in automating netlist generation for analog circuits within circuit design automation. Automating this workflow could accelerate the creation of finetuned LLMs for analog circuit design and verification. We identify key challenges in this automation and evaluate the multi-modal capabilities of state-of-the-art LLMs, particularly GPT-4, to address these issues. We propose a three-step workflow to overcome current limitations: labeling analog circuits, prompt tuning, and netlist verification. This approach aims to create an end-to-end SPICE netlist generator from circuit schematic images, tackling the long-standing hurdle of accurate netlist generation. Our framework demonstrates significant performance improvements, tested on approximately 2,100 schematics of varying complexity. We open-source this solution for community-driven development.

Problem

• Automates SPICE netlist generation
• Enhances analog circuit design
• Leverages AI for verification

Innovation

• Leverages LLMs for SPICE netlists
• End-to-end netlist generator
• Open-source circuit design framework