No Attention, No Problem: DPU-Aware Attention Approximation in Modern YOLO on FPGA

📅 2026-07-14
📈 Citations: 0
Influential: 0
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🤖 AI Summary
This work addresses the challenges of deploying attention-enhanced YOLO models on edge FPGAs, where limited DPU support for certain operators—such as specific activation functions, split operations, and spatial attention mechanisms—hinders simultaneous optimization of accuracy, speed, and energy efficiency. Focusing on AMD FPGA platforms, the study proposes a DPU-aware architectural optimization strategy for YOLO, incorporating operator substitution, replacement of split operations with 1×1 convolutions, DPU-compatible approximations of attention mechanisms, INT8 quantization, and multi-configuration deployment. This approach enables, for the first time, efficient end-to-end inference of modern YOLO variants—including YOLOv26 and YOLOv11—on the Xilinx ZCU104. Experiments demonstrate that YOLOv26n achieves 34.05 and 29.55 FPS on six benchmark datasets for standard and oriented object detection, respectively, with approximately threefold lower power consumption and only a ~5% mAP degradation.
📝 Abstract
Edge-based Artificial Intelligence (AI) acceleration has recently improved progress in real-time object detection. Object detection on edge devices requires a balance between accuracy, speed, and power efficiency. This paper proposes a customized Deep Learning Processor Unit (DPU)-aware architecture for attention-based YOLO variants deployed on AMD FPGAs. Specifically, we evaluate and benchmark YOLOv26 and YOLOv11, two modern attention-based YOLO variants, on the Xilinx ZCU104 across both standard and oriented object detection tasks. We replace unsupported activation functions, substitute split operations with 1x1 convolutions, and approximate the spatial attention mechanism in a DPU-compatible way. All models are then trained and evaluated across six benchmark datasets such as COCO, Pascal VOC, KITTI, DOTA, DIOR-R, and an in-house human presence dataset, and benchmarked across all eight DPU configurations (B512 to B4096) in terms of mAP, FPS, latency, power, and resource utilization. Notably, YOLOv26n and YOLOv26n-OBB deliver the highest end-to-end throughput at 34.05 and 29.55 FPS for standard and oriented detection, respectively, with an average of 5% absolute reduction in accuracy due to quantization while achieving up to approximately 3x lower power consumption compared with the state of the art.
Problem

Research questions and friction points this paper is trying to address.

object detection
attention mechanism
FPGA
DPU
edge AI
Innovation

Methods, ideas, or system contributions that make the work stand out.

DPU-aware
attention approximation
YOLO
FPGA acceleration
edge AI
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