Weight Mapping Properties of a Dual Tree Single Clock Adiabatic Capacitive Neuron

2025-09-15

AI Summary

This work addresses the hardware mapping challenge from artificial neural networks (ANNs) to dual-tree single-clock adiabatic capacitive neuron (DTSC ACN) circuits. We propose a joint optimization framework for weight quantization and capacitive parameter mapping. By analyzing the impact of weight quantization on comparator decision accuracy and integrated circuit (IC) area, we formulate a co-design metric balancing layout efficiency and classification performance. Leveraging TensorFlow/Larq for ANN training, our method achieves functionally equivalent conversion from synaptic weights to physical capacitance values. Experimental evaluation across three representative ANN architectures demonstrates: (1) 100% logical functional equivalence; (2) average chip area reduction of 32.7%; and (3) image classification accuracy improvement of 1.8–2.4 percentage points. These results significantly enhance the energy efficiency and integration density of adiabatic neuromorphic chips.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Natural Language Processing: Learning & Optimization for NLP

Application Category

• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Economics, Online Markets and Human Computation: Data quality aspects of human-annotated datasets
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics

Abstract

Dual Tree Single Clock (DTSC) Adiabatic Capacitive Neuron (ACN) circuits offer the potential for highly energy-efficient Artificial Neural Network (ANN) computation in full custom analog IC designs. The efficient mapping of Artificial Neuron (AN) abstract weights, extracted from the software-trained ANNs, onto physical ACN capacitance values has, however, yet to be fully researched. In this paper, we explore the unexpected hidden complexities, challenges and properties of the mapping, as well as, the ramifications for IC designers in terms accuracy, design and implementation. We propose an optimal, AN to ACN methodology, that promotes smaller chip sizes and improved overall classification accuracy, necessary for successful practical deployment. Using TensorFlow and Larq software frameworks, we train three different ANN networks and map their weights into the energy-efficient DTSC ACN capacitance value domain to demonstrate 100% functional equivalency. Finally, we delve into the impact of weight quantization on ACN performance using novel metrics related to practical IC considerations, such as IC floor space and comparator decision-making efficacy.

Problem

• Mapping software-trained neural network weights to physical capacitance values
• Addressing hidden complexities in weight mapping for energy-efficient analog ICs
• Investigating weight quantization impact on chip size and classification accuracy

Innovation

• Proposes optimal methodology mapping artificial neuron weights
• Demonstrates 100% functional equivalency using TensorFlow and Larq
• Analyzes weight quantization impact with novel IC metrics