๐ค AI Summary
Existing hash functions used in zero-knowledge proofs (ZKPs) suffer from low computational efficiency on general-purpose hardware and inadequate support for specialized hardware acceleration. Method: This paper proposes HashEmAllโthe first systematic FPGA-based hardware acceleration framework for ZK-friendly hash functions, including Griffin, Rescue-Prime, and Reinforced Concrete. It introduces a ZK-optimized arithmetic unit architecture supporting multi-precision finite-field arithmetic and flexible, runtime-switchable algorithm execution, implemented in Verilog RTL on the Xilinx Artix-7 platform. Contribution/Results: Experimental evaluation demonstrates up to 23ร speedup over CPU implementations, significantly improved energy efficiency, and throughput exceeding hundreds of thousands of hashes per second. HashEmAll is compatible with low-cost commercial FPGAs, enabling practical deployment for real-world ZKP circuit generation and verification.
๐ Abstract
Collision-resistant cryptographic hash functions (CRHs) are crucial for security in modern systems but are optimized for standard CPUs. While heavily used in zero-knowledge proof (ZKP) applications, traditional CRHs are inefficient in the ZK domain. ZK-friendly hashes have been developed but struggle on consumer hardware due to a lack of specialized ZK-specific hardware. To address this, we present HashEmAll, a novel collection of FPGA-based realizations of three ZK-friendly hash functions: Griffin, Rescue-Prime, and Reinforced Concrete. Each hash offers different optimization focuses, allowing users to choose based on the constraints of their applications. Through our ZK-optimized arithmetic functions on reconfigurable hardware, HashEmAll outperforms CPU implementations by up to $23 imes$ with lower power consumption and compatibility with accessible FPGAs.