🤖 AI Summary
This work addresses the lack of simulation tools capable of jointly modeling hardware non-idealities in mixed-signal spiking neural networks (SNNs) while enabling system-level design exploration. The authors propose an open-source, hardware-aware SNN simulation framework embedded within PyTorch that, for the first time, integrates LIF, Hodgkin-Huxley (HH), and Axon-Hillock neuron models with non-volatile analog synapses based on floating-gate transistors and ReRAM devices within a unified platform. Crucially, device nonlinearities and non-ideal characteristics are directly incorporated into the training pipeline. The framework supports end-to-end optimization and cross-layer design space exploration, enabling joint evaluation of classification accuracy, silicon area, power consumption, and quantization sensitivity on benchmarks such as N-MNIST, DVS Gesture, and SHD, thereby facilitating multi-objective-constrained search for optimal neuron-synapse configurations.
📝 Abstract
Energy-efficient neuromorphic computing at the edge requires simulation tools that can capture the non-ideal behavior of mixed-signal spiking neural network (SNN) hardware while supporting system-level design exploration. This work presents an open-source hardware-aware simulation framework for mixed-signal SNNs that enables comparative analysis across neuron, synapse and architecture choices. The framework supports multiple neuron models, including Leaky Integrate-and-Fire (LIF), Hodgkin-Huxley (HH) and Axon-Hillock (AH), together with non-volatile analog synapses based on floating-gate transistors and ReRAM devices. By incorporating device-level nonlinearities directly into PyTorch-based training and inference, the tool enables optimization of physical synaptic parameters rather than idealized abstract weights. The framework is evaluated on standard neuromorphic benchmarks, including N-MNIST, DVS Gesture and Spiking Heidelberg Digits (SHD). For each model dataset configuration, it reports classification accuracy together with hardware-oriented metrics such as silicon area, power consumption and quantization sensitivity. These capabilities enable cross-layer design space exploration and help identify neuron-synapse configurations that best satisfy application-specific constraints on accuracy, energy efficiency, area and hardware fidelity.