CktFormalizer: Autoformalization of Natural Language into Circuit Representations

2026-05-08

AI Summary

This work addresses the high failure rate of natural language–generated hardware descriptions during synthesis or tape-out, often caused by bit-width mismatches, combinational loops, or incomplete logic. It presents the first integration of dependent types and formal proof into a closed-loop hardware generation pipeline, leveraging Lean 4 to construct a verifiable hardware description language that guides large language models to produce type-safe and provably correct circuit code. By exposing design flaws at compile time, the approach achieves a backend implementation success rate of 95–100%, matches hand-written Verilog in simulation pass rates across three major benchmarks, automatically completes functional equivalence verification, and yields up to 35% area reduction and 30% power savings.

Abstract

LLMs can generate hardware descriptions from natural language specifications, but the resulting Verilog often contains width mismatches, combinational loops, and incomplete case logic that pass syntax checks yet fail in synthesis or silicon. We present CktFormalizer, a framework that redirects LLM-driven hardware generation through a dependently-typed HDL embedded in Lean 4. Lean serves three roles: (i) type checker:dependent types encode bit-width constraints, case coverage, and acyclicity, turning hardware defects into compile-time errors that guide iterative repair; (ii) correctness firewall:compiled designs are structurally free of defects that cause silent backend failures (the baseline loses 20% of correct designs during synthesis and routing; CktFormalizer preserves all of them); (iii) proof assistant:the agent constructs machine-checked equivalence proofs over arbitrary input sequences and parameterized widths, beyond the reach of bounded SMT-based checking. On VerilogEval (156 problems), RTLLM (50 problems), and ResBench (56 problems), CktFormalizer achieves simulation pass rates competitive with direct Verilog generation while delivering substantially higher backend realizability: 95--100% of compiled designs complete the full synthesis, place-and-route, DRC, and LVS flow. A closed-loop PPA optimization stage yields up to 35% area reduction and 30% power reduction through validated architecture exploration, with automated theorem proof ensuring that each optimized variant remains functionally equivalent to its formal specification.

Problem

• hardware generation
• Verilog defects
• synthesis failure
• natural language to circuit
• backend realizability

Innovation

• dependently-typed HDL
• autoformalization
• hardware correctness
• machine-checked proofs
• PPA optimization