Effective and Memory-Efficient Alternatives to ECC for Reliable Large-Scale DNNs

2026-05-08

AI Summary

This work addresses the vulnerability of deep neural networks to memory transient faults in safety-critical applications, where conventional error-correcting codes like SECDED incur substantial hardware overhead. The authors propose two lightweight protection mechanisms: MSET selectively hardens the most critical parameter bits in CNNs and Vision Transformers (ViTs) through vulnerability analysis, while CEP offers fine-grained, full-parameter protection. Notably, they demonstrate for the first time that safeguarding only the most significant exponent bit of FP16/FP32 floating-point numbers significantly enhances ViT reliability. Experimental results show that the proposed approaches enable up to 10× higher tolerance to bit error rates on large-scale CNNs and ViTs, reduce area overhead by 3.5×, accelerate decoding by 7×, and achieve superior reliability compared to SECDED—all without additional storage cost.

Abstract

Modern Deep Learning (DL) workloads are increasingly deployed in safety-critical domains, such as automotive systems and hyperscale data centers, where transient hardware faults pose a serious threat to system reliability. These workloads are highly memory-intensive, and their correct functionality strongly depends on model parameters stored in memory, which are typically protected using Error Correction Codes (ECCs). In this work, we study ECC's impact on such models and propose two lightweight alternatives to ECCs that achieve superior reliability. The first approach, MSET, selectively hardens the most vulnerable bits in CNN and ViT parameters, while the second approach, CEP, provides fine-grained protection for all parameter bits. Experimental results demonstrate that both methods significantly enhance the reliability of large CNNs and ViTs, mostly outperforming conventional Single Error Detection Double Error Correction (SECDED) ECC schemes, with no memory overhead and, in fact, with considerably lower area and delay characteristics when compared to SECDEC. Experimental results indicate that ViTs can be effectively protected by merely protecting their highest exponent bits in FP16 and FP32 representations. Furthermore, applying the CEP technique can guarantee the resilience of DNNs by up to one order of magnitude higher BERs, with a 3.5x lower area overhead and 7x faster decoder compared to SECDED ECC.

Problem

• Deep Neural Networks
• Hardware Faults
• Error Correction Codes
• Memory Reliability
• Safety-Critical Systems

Innovation

• ECC alternatives
• memory-efficient reliability
• selective bit hardening
• fine-grained error protection
• DNN fault tolerance