Towards a Cryogenic CMOS-Memristor Neural Decoder for Quantum Error Correction

2024-09-15

International Conference on Quantum Computing and Engineering

AI Summary

To address the urgent need for real-time, ultra-low-power decoding in quantum error correction, this work presents a neuromorphic decoder chip designed for cryogenic operation at 1.2 K. The chip integrates 180-nm CMOS with metal-oxide memristors in an in-memory computing architecture. It demonstrates, for the first time at 1.2 K, stable analog sigmoid and threshold activation functions, as well as reliable spiking responses, using memristive crossbar arrays. The design supports a fully analog three-layer neural decoding structure—input–recurrent–output—and exhibits functional consistency across a broad temperature range (300 K to 1.2 K). Experimental results confirm that activation function shape, spiking dynamics, and power consumption retain room-temperature-level stability at cryogenic temperatures. This work establishes the first viable cryogenic integrated circuit solution for scalable, ultra-low-power, real-time hardware decoding in quantum error correction.

Technology Category

• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Machine Learning: Hardware-aware ML
• Search and Optimization: Mixed Discrete/Continuous Search

Application Category

• Economics, Online Markets and Human Computation: Data quality aspects of human-annotated datasets
• Security and Privacy: Applications of cryptography
• Search and Retrieval-Augmented AI: Agentic search

Abstract

This paper presents a novel approach utilizing a scalable neural decoder application-specific integrated circuit (ASIC) based on metal oxide memristors in a 180nm CMOS technology. The ASIC architecture employs in-memory computing with memristor crossbars for efficient vector-matrix multiplications (VMM). The ASIC decoder architecture includes an input layer implemented with a VMM and an analog sigmoid activation function, a recurrent layer with analog memory, and an output layer with a VMM and a threshold activation function. Cryogenic characterization of the ASIC is conducted, demonstrating its performance at both room temperature and cryogenic temperatures down to 1.2K. Results indicate stable activation function shapes and pulse responses at cryogenic temperatures. Moreover, power consumption measurements reveal consistent behavior at room and cryogenic temperatures. Overall, this study lays the foundation for developing efficient and scalable neural decoders for quantum error correction in cryogenic environments.

Problem

• Quantum Computing
• Error Correction
• Performance Improvement

Innovation

• ASIC chip design
• quantum error correction
• neuromorphic decoder