Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V Processors

2025-09-19

AI Summary

To address the low efficiency of manual exploration and the difficulty of balancing performance gains against hardware overhead in RISC-V custom instruction design, this paper proposes CIDRE—a fully automated toolchain for end-to-end custom instruction synthesis, from dynamic hotspot analysis and pattern extraction to automatic generation of synthesizable nML hardware descriptions. Methodologically, CIDRE integrates a microarchitecture-aware instruction identification mechanism with an ASIP co-design flow, enabling joint evaluation of performance, area, and power. Evaluated on Embench and MiBench benchmarks, it achieves an average speedup of 1.83× (up to 2.47×) with custom instruction area overhead ≤24%, significantly outperforming existing manual or semi-automated approaches. Key contributions include: (1) the first end-to-end, microarchitecture-aware framework for automated custom instruction generation; (2) support for evaluatable and synthesizable nML output; and (3) empirical validation of the approach’s practicality and scalability under energy-efficiency and area constraints.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Agent Architectures
• Knowledge Representation and Reasoning: Automated Reasoning and Theorem Proving

Application Category

• User Modeling, Personalization and Recommendation: Fairness-aware retrieval and ranking
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics

Abstract

An Application-Specific Instruction Set Processor(ASIP) is a specialized microprocessor that provides a trade-off between the programmability of a General Purpose Processor (GPP) and the performance and energy-efficiency of dedicated hardware accelerators. ASIPs are often derived from off-the-shelf GPPs extended by custom instructions tailored towards a specific software workload. One of the most important challenges of designing an ASIP is to find said custom instructions that help to increase performance without being too costly in terms of area and power consumption. To date, solving this challenge is relatively labor-intensive and typically performed manually. Addressing the lack of automation, we present Custom Instruction Designer for RISC-V Extensions (CIDRE), a front-to-back tool for ASIP design. CIDRE automatically analyzes hotspots in RISC-V applications and generates custom instruction suggestions with a corresponding nML description. The nML description can be used with other electronic design automation tools to accurately assess the cost and benefits of the found suggestions. In a RISC-V benchmark study, we were able to accelerate embedded benchmarks from Embench and MiBench by up to 2.47x with less than 24% area increase. The entire process was conducted completely automatically.

Problem

• Automating custom instruction design for RISC-V ASIPs
• Balancing performance gains with area and power costs
• Eliminating manual labor in processor customization process

Innovation

• Automated hotspot analysis for RISC-V applications
• Automatic custom instruction generation with nML description
• Complete ASIP design automation with accurate cost assessment