Late Breaking Result: FPGA-Based Emulation and Fault Injection for CNN Inference Accelerators

2025-01-22

AI Summary

Evaluating the robustness of CNN hardware accelerators under physical faults remains challenging due to the lack of high-fidelity, end-to-end hardware-level fault simulation methodologies. Method: This work proposes a full-flow FPGA-based fault-tolerant simulation framework, implemented on a Zynq UltraScale+ SoC. It instantiates a customized ResNet-18 inference accelerator based on the NVDLA architecture, integrates RTL-level targeted fault injection logic, and leverages a Tengine-driven automated hardware generation flow. Contribution/Results: To the best of our knowledge, this is the first FPGA-level end-to-end fault-tolerant simulation for an NVDLA-compatible accelerator. Compared with conventional software simulation, the platform accelerates fault impact analysis—particularly for multiply-accumulate units—by over one order of magnitude. It quantitatively characterizes the degradation in image classification accuracy induced by single-point multiplier faults. The framework establishes a reproducible, high-fidelity hardware verification paradigm for architectural optimization and fault-resilient design of reliable CNN accelerators.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: Adversarial Attacks & Robustness
• Natural Language Processing: Safety and Robustness

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• Search and Retrieval-Augmented AI: Retrieval-Augmented Generation (RAG) and multi-modal RAG
• Security and Privacy: Large-scale security measurements

Abstract

A new field programmable gate array (FPGA)-based emulation platform is proposed to accelerate fault tolerance analysis of inference accelerators of convolutional neural networks (CNN). For a given CNN model, hardware accelerator architecture, and FT analysis target, an FPGA-based CNN implementation is generated (with the help of the Tengine framework), and fault injection logic is added. In our first case study, we report how the classification accuracy drop depends on the faults injected into multipliers used in Multiply-and-Accumulate Units of NVDLA inference accelerator executing ResNet-18 CNN. The FT analysis emulated on Zynq UltraScale+ SoC is an order of magnitude faster than software emulation.

Problem

• CNN accelerators
• robustness evaluation
• performance degradation

Innovation

• FPGA
• CNN Accelerator
• Error Resilience