🤖 AI Summary
To address the challenge of simultaneously achieving high decoding accuracy and low power consumption in 5G LDPC decoders, this work proposes a check-node-aware, region-specific coarse quantization co-design framework. Methodologically, it integrates information-bottleneck-driven message compression, reliability-aligned rate-adaptive region partitioning, and degree-sensitive message separation with layer-level scheduling optimization, yielding a rate-compatible 2-bit quantized architecture. Key contributions include: (i) the first introduction of a check-node-aware variable-node quantization mechanism; (ii) a scalable, rate-dimension-aligned region model; and (iii) lossless 2-bit decoding—i.e., zero performance degradation versus full-precision baselines. Experimental results demonstrate up to 0.4 dB decoding gain improvement, a 35% reduction in average iteration count, a 100% increase in area efficiency, and 2-bit decoding performance on par with conventional 4-bit implementations.
📝 Abstract
This paper presents novel techniques for improving the error correction performance and reducing the complexity of coarsely quantized 5G-LDPC decoders. The proposed decoder design supports arbitrary message-passing schedules on a base-matrix level by modeling exchanged messages with entry-specific discrete random variables. Variable nodes (VNs) and check nodes (CNs) involve compression operations designed using the information bottleneck method to maximize preserved mutual information between code bits and quantized messages. We introduce alignment regions that assign the messages to groups with aligned reliability levels to decrease the number of individual design parameters. Group compositions with degree-specific separation of messages improve performance by up to 0.4 dB. Further, we generalize our recently proposed CN-aware quantizer design to irregular LDPC codes and layered schedules. The method optimizes the VN quantizer to maximize preserved mutual information at the output of the subsequent CN update, enhancing performance by up to 0.2 dB. A schedule optimization modifies the order of layer updates, reducing the average iteration count by up to 35 %. We integrate all new techniques in a rate-compatible decoder design by extending the alignment regions along a rate-dimension. Our complexity analysis shows that 2-bit decoding can double the area efficiency over 4-bit decoding without sacrificing performance.