Voyager: An End-to-End Framework for Design-Space Exploration and Generation of DNN Accelerators

2025-09-18

AI Summary

Low automation, limited parameterization, weak quantization support, and fragmented compiler toolchains hinder DNN accelerator hardware design. To address these challenges, this paper proposes the first end-to-end, HLS-based automatic accelerator generation framework. It unifies architecture exploration, configurable hardware synthesis, and native PyTorch model compilation—enabling co-optimization of on-chip buffer hierarchies, compute unit configurations, and off-chip memory bandwidth. The framework introduces novel support for user-defined data formats and micro-scale quantization. Evaluated on vision and language models, generated accelerators achieve 99.8% resource utilization, reduce latency by 61% and area by 56% versus baseline designs, while matching hand-optimized implementations in performance. This advances industrial-grade DNN accelerator design by significantly improving both efficiency and configurability.

Technology Category

• Machine Learning: Hardware-aware ML
• Natural Language Processing: Code Generation / Program Synthesis from Natural Language
• Computer Vision: Learning & Optimization for CV

Application Category

• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines

Abstract

While deep neural networks (DNNs) have achieved state-of-the-art performance in fields from computer vision to natural language processing, efficiently running these computationally demanding models requires hardware accelerators. However, designing these accelerators is a time-consuming, labor-intensive process that does not scale well. While prior efforts have sought to automate DNN accelerator generation, they offer limited parameterization, cannot produce high-performance, tapeout-ready designs, provide limited support for datatypes and quantization schemes, and lack an integrated, end-to-end software compiler. This work proposes Voyager, a high-level synthesis (HLS)-based framework for design space exploration (DSE) and generation of DNN accelerators. Voyager overcomes the limitations of prior work by offering extensive configurability across technology nodes, clock frequencies, and scales, with customizable parameters such as number of processing elements, on-chip buffer sizes, and external memory bandwidth. Voyager supports a wider variety of datatypes and quantization schemes versus prior work, including both built-in floating-point, posit and integer formats, as well as user-defined formats with both per-tensor scaling and microscaling quantization. Voyager's PyTorch-based compiler efficiently maps networks end-to-end on the generated hardware, with support for quantization, fusion, and tiling. We evaluate Voyager on state-of-the-art vision and language models. Voyager enables fast DSE with full-dataset accuracy evaluation for datatypes and quantization schemes. Generated designs achieve a high utilization across models and scales, up to 99.8%, and outperform prior generators with up to 61% lower latency and 56% lower area. Compared to hand-optimized accelerators, Voyager achieves comparable performance, while offering much greater automation in design and workload mapping.

Problem

• Automating DNN accelerator design to overcome manual inefficiency
• Providing extensive configurability for high-performance tapeout-ready accelerators
• Enabling end-to-end mapping with diverse datatype and quantization support

Innovation

• HLS-based framework for DNN accelerator generation
• Extensive configurability across technology nodes and scales
• PyTorch compiler with quantization and fusion support