🤖 AI Summary
NP-hard combinatorial optimization problems resist exact polynomial-time solutions.
Method: This work proposes a hardware-accelerated approximate solving framework based on CMOS oscillator networks. It unifies diverse NP problems—including graph coloring, Max-Cut, and the Traveling Salesman Problem—into first-order or multi-state Potts Hamiltonians, and implements a three-state asymmetric weighted oscillator circuit leveraging multistable dynamics for efficient energy minimization.
Contribution/Results: To our knowledge, this is the first systematic mapping of heterogeneous NP problems onto a single, unified oscillator network architecture, fabricated in standard CMOS technology to enable hardware-efficient parallel optimization. Experiments on benchmark instances demonstrate polynomial-time convergence to high-quality approximate solutions, with significantly faster convergence and superior solution quality compared to conventional heuristic algorithms. The approach establishes a scalable analog-computing paradigm for large-scale combinatorial optimization.
📝 Abstract
Efficiently optimizing Nondeterministic Polynomial time (NP) problems in polynomial time has profound implications in many domains. CMOS oscillator networks have been shown to be effective and efficient in approximating certain NP-hard problems such as minimization of Potts Hamiltonian, and computational complexity theory guarantees that any NP problem can be reduced to it. In this paper, we formulate a variety of NP problems using first-order and multi-phase Potts Hamiltonian. We also propose a 3-state asymmetrically weighted oscillator optimizer design to optimize the problems. Building on existing knowledge in CMOS design, our proposed algorithms offer a promising pathway for large-scale optimization of NP problems.