Scaling Routers with In-Package Optics and High-Bandwidth Memories

2026-02-11

AI Summary

This work addresses the limitations of conventional Internet routers—constrained by power consumption, bandwidth, and packaging integration bottlenecks—as they scale toward petabit-per-second rates. The authors propose a novel single-package petabit-scale router architecture that integrates heterogeneous chiplets, in-package optical interconnects, and high-bandwidth memory (HBM). A key innovation is a passive, spatially split parallel switching fabric that eliminates intermediate optical-electrical-optical conversions. To enable efficient shared memory access, they design an HBM cyclically interleaved frame-packing algorithm. Under backbone traffic patterns, the architecture achieves fine-grained scheduling performance through coarse-grained load balancing, delivering petabit-per-second routing capacity within a single package. The study further identifies power consumption as the primary bottleneck for future scalability.

Technology Category

• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Search and Optimization: Distributed Search
• Machine Learning: Hardware-aware ML

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Security and Privacy: Large-scale security measurements

Abstract

This paper aims to apply two major scaling transformations from the computing packaging industry to internet routers: the heterogeneous integration of high-bandwidth memories (HBMs) and chiplets, as well as in-package optics. We propose a novel internet router architecture that employs these technologies to achieve a petabit/sec router within a single integrated package. At the top-level, we introduce a novel split-parallel switch architecture that spatially divides (without processing) the incoming fibers and distributes them across smaller independent switches without intermediate OEO conversions or fine-tuned per-packet load-balancing. This passive spatial division enables scaling at the cost of a coarser traffic load balancing. Yet, through extensive evaluations of backbone network traffic, we demonstrate that differences with fine-tuned approaches are small. In addition, we propose a novel HBM-based shared-memory architecture for the implementation of the smaller independent switches, and we introduce a novel parallel frame interleaving algorithm that packs traffic into frames so that HBM banks are accessed at peak HBM data rates in a cyclical interleaving manner. We further discuss why these new technologies represent a paradigm shift in the design of future internet routers. Finally, we emphasize that power consumption may constitute the primary bottleneck to scaling.

Problem

• router scaling
• in-package optics
• high-bandwidth memory
• petabit switching
• power bottleneck

Innovation

• in-package optics
• high-bandwidth memory (HBM)
• split-parallel switch architecture
• chiplet integration
• parallel frame interleaving