DRAMPyML: A Formal Description of DRAM Protocols with Timed Petri Nets

2026-02-11

AI Summary

This work addresses the growing complexity of JEDEC DRAM protocols, which renders traditional finite-state machines inadequate for accurately capturing concurrent multi-bank operations and intricate timing constraints, thereby hindering comprehension and verification. To overcome these limitations, the paper introduces timed Petri nets—a formalism well-suited for modeling concurrency and real-time behavior—into DRAM protocol specification for the first time. Leveraging Python, the authors develop an executable formal model that precisely encodes the protocol’s parallelism and timing semantics. This model not only substantially enhances the clarity and efficiency of protocol understanding but also enables rigorous correctness verification of DRAM controllers (RTL), DRAM logic, and memory simulators, while supporting evaluation of key performance metrics—capabilities unattainable with conventional state-machine-based approaches.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Planning, Routing, and Scheduling: Model-Based Reasoning

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs

Abstract

The JEDEC committee defines various domain-specific DRAM standards. These standards feature increasingly complex and evolving protocol specifications, which are detailed in timing diagrams and command tables. Understanding these protocols is becoming progressively challenging as new features and complex device hierarchies are difficult to comprehend without an expressive model. While each JEDEC standard features a simplified state machine, this state machine fails to reflect the parallel operation of memory banks. In this paper, we present an evolved modeling approach based on timed Petri nets and Python. This model provides a more accurate representation of DRAM protocols, making them easier to understand and directly executable, which enables the evaluation of interesting metrics and the verification of controller RTL models, DRAM logic and memory simulators.

Problem

• DRAM protocols
• JEDEC standards
• protocol complexity
• parallel memory banks
• formal modeling

Innovation

• Timed Petri Nets
• DRAM protocols
• formal modeling
• parallel bank operation
• executable specification