Orthrus: Dual-Loop Automated Framework for System-Technology Co-Optimization

2025-09-16

AI Summary

Facing the challenges of cross-layer information fragmentation and inefficient design-space exploration in system-technology co-optimization (STCO) under Moore’s Law slowdown, this paper proposes Orthrus—a dual-loop collaborative framework. Orthrus employs an outer loop driven by system-level statistical profiling to identify critical units and prioritize optimization targets, while an inner loop leverages Pareto-frontier direction guidance to steer process-parameter search. It innovatively integrates Bayesian optimization—used to explore the system-level Pareto frontier—with a neural-network-enhanced differential evolution algorithm—employed for unit-level parameter optimization—thereby establishing a closed-loop feedback between system architecture and technology. Evaluated on a 7-nm process, Orthrus achieves either a 12.5% latency reduction at equal power or a 61.4% power saving at equal latency versus the baseline, significantly expanding the STCO energy-efficiency Pareto frontier.

Technology Category

• Search and Optimization: Distributed Search
• Machine Learning: Optimization
• Constraint Satisfaction and Optimization: Constraint Optimization

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Experiences and lessons learnt from Web-based algorithms and system deployments
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines

Abstract

With the diminishing return from Moore's Law, system-technology co-optimization (STCO) has emerged as a promising approach to sustain the scaling trends in the VLSI industry. By bridging the gap between system requirements and technology innovations, STCO enables customized optimizations for application-driven system architectures. However, existing research lacks sufficient discussion on efficient STCO methodologies, particularly in addressing the information gap across design hierarchies and navigating the expansive cross-layer design space. To address these challenges, this paper presents Orthrus, a dual-loop automated framework that synergizes system-level and technology-level optimizations. At the system level, Orthrus employs a novel mechanism to prioritize the optimization of critical standard cells using system-level statistics. It also guides technology-level optimization via the normal directions of the Pareto frontier efficiently explored by Bayesian optimization. At the technology level, Orthrus leverages system-aware insights to optimize standard cell libraries. It employs a neural network-assisted enhanced differential evolution algorithm to efficiently optimize technology parameters. Experimental results on 7nm technology demonstrate that Orthrus achieves 12.5% delay reduction at iso-power and 61.4% power savings at iso-delay over the baseline approaches, establishing new Pareto frontiers in STCO.

Problem

• Addressing information gap across VLSI design hierarchies
• Navigating expansive cross-layer system-technology co-optimization space
• Developing efficient automated framework for STCO methodology

Innovation

• Dual-loop automated system-technology co-optimization framework
• Bayesian optimization with Pareto frontier normal directions
• Neural network-assisted enhanced differential evolution algorithm