HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers

2025-01-09

AI Summary

Large language models (LLMs) suffer from severe hallucinations, substantial semantic deviations, and misalignment with hardware engineers’ domain-specific expression conventions when generating Verilog code. To address these challenges, this paper proposes an HDL-oriented code generation optimization framework. Its core contributions are threefold: (1) the first fine-grained Verilog hallucination taxonomy; (2) a symbolic-modality–to–natural-language chain-of-thought (CoT) translation mechanism—leveraging truth tables, state diagrams, and other formal representations—to enhance logical interpretability; and (3) an instruction-code co-augmentation paradigm grounded in real-world RTL engineering practices. Evaluated on VerilogEval and RTLLM benchmarks, our method significantly outperforms state-of-the-art approaches, achieving substantial gains in functional correctness. All code and datasets are publicly released.

Technology Category

• Natural Language Processing: Code Generation / Program Synthesis from Natural Language
• Machine Learning: Large Multimodal Models (LMMs)
• Computer Vision: Visual Reasoning & Symbolic Representations

Application Category

• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Search and Retrieval-Augmented AI: Large language models for search

Abstract

Recently, the use of large language models (LLMs) for Verilog code generation has attracted great research interest to enable hardware design automation. However, previous works have shown a gap between the ability of LLMs and the practical demands of hardware description language (HDL) engineering. This gap includes differences in how engineers phrase questions and hallucinations in the code generated. To address these challenges, we introduce HaVen, a novel LLM framework designed to mitigate hallucinations and align Verilog code generation with the practices of HDL engineers. HaVen tackles hallucination issues by proposing a comprehensive taxonomy and employing a chain-of-thought (CoT) mechanism to translate symbolic modalities (e.g. truth tables, state diagrams, etc.) into accurate natural language descriptions. Furthermore, HaVen bridges this gap by using a data augmentation strategy. It synthesizes high-quality instruction-code pairs that match real HDL engineering practices. Our experiments demonstrate that HaVen significantly improves the correctness of Verilog code generation, outperforming state-of-the-art LLM-based Verilog generation methods on VerilogEval and RTLLM benchmark. HaVen is publicly available at https://github.com/Intelligent-Computing-Research-Group/HaVen.

Problem

• Large Language Models
• Verilog Code Generation
• Accuracy and Usability Improvement

Innovation

• HaVen
• Verilog code generation
• diagram interpretation