Implementing and Optimizing an Open-Source SD-card Host Controller for RISC-V SoCs

2026-03-12

AI Summary

This work addresses the lack of efficient non-volatile storage support in open-source RISC-V SoCs by integrating and optimizing an SDHCI-compliant SD card host controller into the Cheshire platform. Through a hardware-software co-design approach that leverages the memory characteristics of the CVA6 processor and Linux driver behavior, this study achieves high-performance SD card support for the first time in a fully open-source RISC-V system while avoiding the cache and pipeline flush overhead induced by RISC-V fence instructions. The optimized implementation attains a read/write throughput of 11.1 MB/s—approaching the theoretical limit of the SD interface (12.5 MB/s)—and delivers a 6.5× performance improvement over conventional SPI-based solutions.

Technology Category

• Computer Vision: Learning & Optimization for CV
• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Security and Privacy: Large-scale security measurements
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics

Abstract

Recent announcements have shown the viability of end-to-end open-source (OS) Linux-capable RISC-V systems on chip (SoCs). However, practical application and software development platforms require efficient non-volatile storage, which is not adequately served by common SPI-based interfaces due to their limited throughput. Secure Digital (SD) cards are the de facto standard storage medium for embedded Linux systems; efficient SD host controller (SDHC) integration is thus essential for open-source RISC-V platforms. We present an OS SD host controller interface (SDHCI) peripheral integrated into the end-to-end OS Cheshire RISC-V SoC platform. The controller and its software stack are designed with full awareness of CVA6's memory system and Linux driver behavior; during evaluation, we identify a significant performance bottleneck caused by the RISC-V memory model and CVA6's implementation of the fence instruction, which flushes the pipeline and data cache on memory-mapped register accesses when cache management operations (CMOs) are unavailable. By customizing the driver's register access paths and avoiding unnecessary fences, we substantially reduced this overhead. Our fully OS controller achieves up to 11.1 MB/s throughput, approaching the 12.5 MB/s limit of the SD interface and providing up to 6.5 times the throughput of SPI-based storage.

Problem

• RISC-V
• SD host controller
• open-source SoC
• non-volatile storage
• Linux-capable

Innovation

• RISC-V
• SDHCI
• open-source SoC
• memory model optimization
• cache management