🤖 AI Summary
Micro- and nano-drones face severe constraints in computational capability and power consumption, hindering deployment of high-accuracy visual-inertial odometry (VIO).
Method: This work proposes a lightweight, efficient downward-looking VIO system tailored for the RISC-V ultra-low-power SoC GAP9. It fuses SuperPoint, ORB, and PX4FLOW for feature extraction and tracking, incorporates rigid-body motion constraints to enhance planar pose estimation accuracy, and achieves hardware co-optimization via model quantization, computation graph optimization, and RISC-V parallel instruction scheduling.
Contribution/Results: To our knowledge, this is the first real-time VIO implementation on GAP9. The optimized ORB tracker reduces RMSE by an average factor of 3.65; PX4FLOW achieves ORB-level accuracy at translational velocities below 24 pixels/frame while exhibiting lower latency. This work bridges the practical gap between high-precision VIO algorithms and microcontroller-class hardware.
📝 Abstract
Visual Inertial Odometry (VIO) is a widely used computer vision method that determines an agent's movement through a camera and an IMU sensor. This paper presents an efficient and accurate VIO pipeline optimized for applications on micro- and nano-UAVs. The proposed design incorporates state-of-the-art feature detection and tracking methods (SuperPoint, PX4FLOW, ORB), all optimized and quantized for emerging RISC-V-based ultra-low-power parallel systems on chips (SoCs). Furthermore, by employing a rigid body motion model, the pipeline reduces estimation errors and achieves improved accuracy in planar motion scenarios. The pipeline's suitability for real-time VIO is assessed on an ultra-low-power SoC in terms of compute requirements and tracking accuracy after quantization. The pipeline, including the three feature tracking methods, was implemented on the SoC for real-world validation. This design bridges the gap between high-accuracy VIO pipelines that are traditionally run on computationally powerful systems and lightweight implementations suitable for microcontrollers. The optimized pipeline on the GAP9 low-power SoC demonstrates an average reduction in RMSE of up to a factor of 3.65x over the baseline pipeline when using the ORB feature tracker. The analysis of the computational complexity of the feature trackers further shows that PX4FLOW achieves on-par tracking accuracy with ORB at a lower runtime for movement speeds below 24 pixels/frame.