Finesse: An Agile Design Framework for Pairing-based Cryptography via Software/Hardware Co-Design

2025-09-12

AI Summary

Traditional hardware designs for pairing-based cryptography (PBC) suffer from long development cycles and poor trade-offs between flexibility and performance due to frequent algorithmic updates. To address this, this paper proposes a software-hardware co-design agile framework. It introduces a compiler-driven co-optimization loop, integrating modular hardware abstraction with multi-granularity simulation to enable rapid algorithm iteration and design-space exploration across elliptic curve families and architectural variants. Experimental results demonstrate that, compared to state-of-the-art flexible frameworks, our approach achieves a 34× improvement in throughput and a 6.2× gain in area efficiency. Against the best non-flexible ASIC implementations, it delivers 3× higher throughput and 3.2× better area efficiency. These advances significantly enhance the efficiency and reconfigurability of PBC accelerators.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Sampling/Simulation-based Search
• Cognitive Modeling & Cognitive Systems: Agent Architectures

Application Category

• Security and Privacy: Applications of cryptography
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs

Abstract

Pairing-based cryptography (PBC) is crucial in modern cryptographic applications. With the rapid advancement of adversarial research and the growing diversity of application requirements, PBC accelerators need regular updates in algorithms, parameter configurations, and hardware design. However, traditional design methodologies face significant challenges, including prolonged design cycles, difficulties in balancing performance and flexibility, and insufficient support for potential architectural exploration. To address these challenges, we introduce Finesse, an agile design framework based on co-design methodology. Finesse leverages a co-optimization cycle driven by a specialized compiler and a multi-granularity hardware simulator, enabling both optimized performance metrics and effective design space exploration. Furthermore, Finesse adopts a modular design flow to significantly shorten design cycles, while its versatile abstraction ensures flexibility across various curve families and hardware architectures. Finesse offers flexibility, efficiency, and rapid prototyping, comparing with previous frameworks. With compilation times reduced to minutes, Finesse enables faster iteration cycles and streamlined hardware-software co-design. Experiments on popular curves demonstrate its effectiveness, achieving $34 imes$ improvement in throughput and $6.2 imes$ increase in area efficiency compared to previous flexible frameworks, while outperforming state-of-the-art non-flexible ASIC designs with a $3 imes$ gain in throughput and $3.2 imes$ improvement in area efficiency.

Problem

• Addresses prolonged design cycles in pairing-based cryptography accelerators
• Solves difficulties balancing performance and flexibility in PBC hardware
• Enables efficient architectural exploration for diverse cryptographic requirements

Innovation

• Software/hardware co-design methodology
• Compiler-driven co-optimization cycle
• Modular design flow abstraction