Noise-Aware Synthesis of Quantum LDPC Encoder Circuits via Two-Sided Hamming Descent

2026-07-05

AI Summary

This work addresses the challenges of high redundancy, noise sensitivity, and hardware mapping difficulties in quantum LDPC encoder circuits, which hinder efficient encoded state preparation in fault-tolerant quantum computing. The authors reformulate encoder construction as a reversible linear circuit resynthesis problem and introduce a bidirectional Hamming descent optimization method. By integrating CNOT block resynthesis, hardware-aware routing, and noise-aware scheduling strategies, the proposed approach significantly reduces circuit size and depth while respecting hardware constraints. Experimental results demonstrate an average 53.8% reduction in gate count across various CSS-LDPC codes—reaching up to 68% for Bivariate Bicycle codes—with post-routing two-qubit circuit depth reduced by as much as 71%. Furthermore, encoded state preparation failure rates decrease by up to 13.7%, yielding substantially improved fidelity.

Abstract

Quantum low-density parity-check (LDPC) codes are a promising route to fault-tolerant quantum computation, but their use requires efficient preparation of encoded states. Standard encoder constructions generate circuits through fixed algebraic procedures, yet the resulting circuit can contain substantial redundancy. We formulate LDPC encoder preparation as a circuit-resynthesis problem: given the linear-reversible matrix implemented by the encoder's CNOT block, we seek a lower-cost equivalent circuit that can be routed efficiently on the target hardware and which mitigates noise. We propose a novel optimization approach referred as two-sided Hamming descent and a noise-aware optimization pipeline for this task. Across several families of Calderbank-Shor-Steane (CSS) LDPC encoders, including Bivariate Bicycle, hypergraph-product, and entanglement-assisted codes, the proposed pipeline produces substantially smaller and shallower encoder circuits than the standard constructions and the synthesis baselines considered, cutting gate counts by 53.8% in aggregate across the benchmark and by up to 68% on the Bivariate Bicycle family. The gains remain visible after routing, where the two-qubit depth is reduced by up to 71% and translate into higher-fidelity state preparation under circuit-level noise. On the Bivariate Bicycle family, live-range scheduling further reduces routed preparation failure by up to 13.7% without adding two-qubit gates to the selected circuit. These results indicate that encoder-matrix resynthesis, combined with hardware-calibrated selection and scheduling, is an effective compiler-level tool for preparing quantum LDPC code states.

Problem

• quantum LDPC codes
• encoder synthesis
• noise-aware optimization
• CNOT circuit
• fault-tolerant quantum computation

Innovation

• quantum LDPC codes
• circuit resynthesis
• two-sided Hamming descent
• noise-aware optimization
• encoder synthesis