SynDCIM: A Performance-Aware Digital Computing-in-Memory Compiler with Multi-Spec-Oriented Subcircuit Synthesis

2024-11-25

arXiv.org

AI Summary

Existing digital compute-in-memory (DCIM) macro designs rely on manual implementation, resulting in low design efficiency and difficulty in simultaneously optimizing power, area, and latency—thus limiting their performance potential. This paper proposes an agile compilation framework tailored for DCIM macros. It introduces a novel multi-specification-guided subcircuit synthesis algorithm that enables end-to-end automatic mapping from performance metrics to physical layout. A scalable, parameterized subcircuit library is constructed to support multi-objective co-optimization. The framework integrates analytical performance modeling, constraint-driven search, and automated layout generation. Implemented in 40 nm CMOS, the compiler achieves MAC throughput and energy efficiency on silicon comparable to state-of-the-art hand-designed macros, while significantly improving overall design quality. Experimental validation confirms both the practicality and advancement of the proposed methodology.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Mixed Discrete/Continuous Search
• Constraint Satisfaction and Optimization: Distributed CSP/Optimization

Application Category

• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Security and Privacy: Large-scale security measurements

Abstract

Digital Computing-in-Memory (DCIM) is an innovative technology that integrates multiply-accumulation (MAC) logic directly into memory arrays to enhance the performance of modern AI computing. However, the need for customized memory cells and logic components currently necessitates significant manual effort in DCIM design. Existing tools for facilitating DCIM macro designs struggle to optimize subcircuit synthesis to meet user-defined performance criteria, thereby limiting the potential system-level acceleration that DCIM can offer. To address these challenges and enable agile design of DCIM macros with optimal architectures, we present SynDCIM, a performance-aware DCIM compiler that employs multi-spec-oriented subcircuit synthesis. SynDCIM features an automated performance-to-layout generation process that aligns with user-defined performance expectations. This is supported by a scalable subcircuit library and a multi-spec-oriented searching algorithm for effective subcircuit synthesis. The effectiveness of SynDCIM is demonstrated through extensive experiments and validated with a test chip fabricated in a 40nm CMOS process. Testing results reveal that designs generated by SynDCIM exhibit competitive performance when compared to state-of-the-art manually designed DCIM macros.

Problem

• DCIM Design
• Performance Requirements
• AI Acceleration

Innovation

• SynDCIM
• DCIM Optimization
• Memory-centric Computing