SABLE: An NDA-Safe Closed-Loop LLM Framework for Analog Circuit Optimization in Industrial EDA Flows

2026-07-04

AI Summary

This work addresses the challenge of leveraging cloud-based large language models (LLMs) for industrial analog circuit optimization while preserving confidentiality of sensitive design data—such as PDKs, schematics, and simulation paths—that cannot be disclosed due to non-disclosure agreements (NDAs). The authors propose the first LLM-EDA closed-loop framework secure under a “curious-but-passive” cloud threat model. Security is ensured through 28 whitelisted SKILL APIs, end-to-end data sanitization, structured Maestro configurations, and a JSON action contract incorporating six machine-verifiable termination conditions. Evaluated on PVT sign-off tasks for an LC-VCO and a two-stage operational amplifier, the framework achieved convergence within 15 iterations at 7/11 and 4/11 LLM checkpoints, respectively, demonstrating that effective circuit optimization remains feasible under stringent privacy constraints.

Abstract

Large language models (LLMs) can propose circuit-optimization decisions, but industrial analog flows cannot expose foundry PDK content, proprietary schematics, absolute simulation paths, or license-bound tool state to a cloud endpoint. We present SABLE (Safe Analog Boundary for LLM-driven EDA), an NDA-safe closed-loop framework that lets LLMs optimize analog circuits through Cadence Virtuoso, Maestro, and Spectre while returning only scrubbed topology intent, numeric metrics, operating-point summaries, and scoped writeback status. "NDA-safe" denotes enforcement under a stated curious-but-passive cloud-provider threat model, not a formal non-interference proof. The framework combines an explicit threat model, a whitelist of 28 scoped SKILL entry points, PDK/path/model scrubbing on every return path, structured Maestro setup and writeback, a strict JSON action contract with six machine-checked stop conditions, and best-so-far state preservation. We evaluate eleven LLM checkpoints from the same documented reset state on two real closed-loop tasks, both run as process-voltage-temperature (PVT) sign-offs across three corners: a 20 GHz LC-VCO tuning-curve task and a two-stage op-amp task. On the LC-VCO task 7 of 11 models pass; on the harder op-amp task, where every metric must hold at the worst corner and a phase-margin gate rejects unstable high-gain points, 4 of 11 pass within a 15-iteration budget. Feedback-path ablations show that removing individual sanitized channels either silently weakens the specification or degrades the search. Model quality differs sharply once the loop requires tool discipline, bias reasoning, and specification repair, yet an NDA-safe boundary still provides enough sanitized feedback for successful analog circuit optimization.

Problem

• analog circuit optimization
• NDA-safe
• large language models
• industrial EDA
• closed-loop framework

Innovation

• NDA-safe
• closed-loop LLM
• analog circuit optimization
• EDA automation
• PDK scrubbing