A Multi-stage Error Diagnosis for APB Transaction

2025-09-03

AI Summary

To address the low efficiency and error-proneness of manual APB transaction error detection in SoC design, this paper proposes a multi-stage automated diagnosis framework based on hierarchical random forests. The method employs a cascaded binary-classifier architecture that prioritizes high-confidence identification of address-related errors, integrating VCD waveform parsing, transaction-level feature extraction, and pre-trained binary classifiers to precisely localize both address- and data-related errors. Its key innovation lies in the first application of hierarchical machine learning to APB protocol debugging, establishing a lightweight, hardware-transaction-semantic-aware diagnostic paradigm. Experimental evaluation demonstrates an overall accuracy of 91.36% and an F1-score of 99.8% for address-error detection, achieving first place in the ICCAD 2025 competition beta phase.

Technology Category

• Knowledge Representation and Reasoning: Diagnosis and Abductive Reasoning
• Machine Learning: Hardware-aware ML
• Reasoning under Uncertainty: Relational Probabilistic Models

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics
• Economics, Online Markets and Human Computation: Data quality aspects of human-annotated datasets

Abstract

Functional verification and debugging are critical bottlenecks in modern System-on-Chip (SoC) design, with manual detection of Advanced Peripheral Bus (APB) transaction errors in large Value Change Dump (VCD) files being inefficient and error-prone. Addressing the 2025 ICCAD Contest Problem D, this study proposes an automated error diagnosis framework using a hierarchical Random Forest-based architecture. The multi-stage error diagnosis employs four pre-trained binary classifiers to sequentially detect Out-of-Range Access, Address Corruption, and Data Corruption errors, prioritizing high-certainty address-related faults before tackling complex data errors to enhance efficiency. Experimental results show an overall accuracy of 91.36%, with near-perfect precision and recall for address errors and robust performance for data errors. Although the final results of the ICCAD 2025 CAD Contest are yet to be announced as of the submission date, our team achieved first place in the beta stage, highlighting the method's competitive strength. This research validates the potential of hierarchical machine learning as a powerful automated tool for hardware debugging in Electronic Design Automation (EDA).

Problem

• Automating APB transaction error diagnosis in SoC design
• Detecting address and data corruption errors efficiently
• Improving hardware debugging with hierarchical machine learning

Innovation

• Hierarchical Random Forest architecture for error diagnosis
• Four pre-trained binary classifiers detect transaction errors
• Prioritizes address faults before complex data errors