Error Detection Schemes for Barrett Reduction of CT-BU on FPGA in Post Quantum Cryptography

2025-09-04

AI Summary

In hardware implementations of Kyber, the Barrett reduction within Cooley–Tukey butterfly units (CT-BUs) is vulnerable to fault-injection attacks, leading to side-channel information leakage. Method: This paper proposes three lightweight recomputation-based fault-detection techniques for Barrett reduction: RENO (operand negation), RESO (operand bit-shift), and the novel RESWO (recomputation with operand permutation). All three methods operate with comparable hardware overhead. Contribution/Results: Each achieves near-100% detection coverage for both single-bit and multi-bit faults. Notably, RESWO significantly reduces critical-path latency, outperforming RENO and RESO in timing efficiency. Implemented and validated on FPGA, the proposed schemes jointly achieve high fault-detection coverage and low latency, providing an efficient, practical reliability assurance mechanism for post-quantum cryptographic hardware accelerators.

Technology Category

• Machine Learning: Hardware-aware ML
• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories
• Knowledge Representation and Reasoning: Diagnosis and Abductive Reasoning

Application Category

• Security and Privacy: Large-scale security measurements
• Responsible Web: Data and user privacy-enhancing technologies for the Web
• User Modeling, Personalization and Recommendation: Attacks and countermeasures in recommendation systems

Abstract

A fault can occur naturally or intentionally. However, intentionally injecting faults into hardware accelerators of Post-Quantum Cryptographic (PQC) algorithms may leak sensitive information. This intentional fault injection in side-channel attacks compromises the reliability of PQC implementations. The recently NIST-standardized key encapsulation mechanism (KEM), Kyber may also leak information at the hardware implementation level. This work proposes three efficient and lightweight recomputation-based fault detection methods for Barrett Reduction in the Cooley-Tukey Butterfly Unit (CT-BU) of Kyber on a Field Programmable Gate Array (FPGA). The CT-BU and Barrett Reduction are fundamental components in structured lattice-based PQC algorithms, including Kyber, NTRU, Falcon, CRYSTALS-Dilithium, etc. This paper introduces a new algorithm, Recomputation with Swapped Operand (RESWO), for fault detection. While Recomputation with Negated Operand (RENO) and Recomputation with Shifted Operand (RESO) are existing methods used in other PQC hardware algorithms. To the best of our knowledge, RENO and RESO have never been used in Barrett Reduction before. The proposed RESWO method consumes a similar number of slices compared to RENO and RESO. However, RESWO shows lesser delay compared to both RENO and RESO. The fault detection efficiency of RESWO, RENO, and RESO is nearly 100%.

Problem

• Detecting faults in Barrett Reduction for PQC algorithms
• Protecting Kyber hardware from intentional fault injections
• Ensuring reliability of FPGA-based lattice cryptography implementations

Innovation

• RESWO algorithm for fault detection
• RENO and RESO applied to Barrett Reduction
• Lightweight recomputation-based FPGA protection methods