MINT: Dynamic-Precision CNN Inference with MSDF Digit-Serial Arithmetic on FPGA

2026-06-30

AI Summary

This work addresses the computational redundancy and energy-efficiency limitations of conventional fixed-precision CNNs on FPGAs by proposing a dynamic-precision inference accelerator based on Most-Significant-Digit-First (MSDF) serial arithmetic. The design integrates redundant signed-digit representation with a budget-constrained greedy search algorithm to dynamically select the minimal feasible integer precision (ranging from INT2 to INT7) per layer and terminate computation early once the target accuracy is achieved. To the best of our knowledge, this is the first integration of MSDF arithmetic with dynamic-precision CNN inference, enabling on-demand precision control. Implemented on a Zynq-7020 FPGA, the approach achieves throughputs of 19.86 and 18.86 GOPS and energy efficiencies of 29.51 and 26.40 GOPS/W for VGG-16 and ResNet-18, respectively, using average precisions of 5.64 and 6.04 bits—yielding over 60% higher energy efficiency than INT8 baselines with less than 2% accuracy loss.

Abstract

We present MINT, a dynamic-precision CNN inference accelerator based on left-to-right (LR) arithmetic. LR arithmetic computes in most-significant-digit-first manner and exposes useful partial results early so that the computation can be terminated once the desired precision is achieved. At the core, there is a MSDF serial-parallel inner-product unit, which uses redundant signed-digit representation to compute each convolution window. A budget-constrained greedy search profiles all convolution layers from INT2 to INT7 and selects the lowest precision per layer while constraining total accuracy loss to within 2\% of the INT8 baseline for VGG-16 and ResNet-18 networks. The design is synthesized on a Xilinx Zynq-7020 at \SI{200}{\mega\hertz}, and uses 5.64 average bits for VGG-16 and 6.04 for ResNet-18, while achieving 19.86 GOPS and 29.51 GOPS/W on VGG-16, and 18.86 GOPS and 26.40 GOPS/W on ResNet-18. This corresponds to 32.6\% and 26.0\% higher throughput and 82.10\% and 62.90\% higher energy efficiency than INT8 with only 1.81\% and 1.96\% drops relative to the INT8 baseline. Compared with representative prior FPGA CNN accelerators considered in this study, MINT delivers the highest energy efficiency among the listed VGG-16 and ResNet-18 designs on Zynq-7020 platform.

Problem

• CNN inference
• dynamic precision
• FPGA acceleration
• energy efficiency
• precision optimization

Innovation

• dynamic-precision
• MSDF arithmetic
• digit-serial computation
• FPGA acceleration
• CNN inference