Maximizing Parallel Execution of Series-Parallel Task Graphs for Safety-Critical Embedded Control

2026-06-30

AI Summary

This study addresses the challenge of meeting real-time requirements for safety-critical embedded control programs, which are inherently constrained by sequential inter-task dependencies on conventional processors. The work introduces a novel formulation of the maximal parallel execution problem under a staged batch processing model as a weighted clique partitioning problem. To solve it efficiently, the authors propose an iterative heuristic algorithm based on Lagrangian pricing (LIH), integrating clique generation, column filtering, repair mechanisms, and hybrid graph-coloring branch-and-bound techniques. The approach achieves optimal solutions in 91.25% of test instances with an average optimality gap of merely 0.073%, while requiring only 18.19 milliseconds on average—yielding speedups of several orders of magnitude over exact baselines. The method has been successfully validated in an end-to-end optimization pipeline translating PLC ladder diagrams to FPGA implementations.

Abstract

Safety-critical embedded control programs must complete each control cycle within a bounded period. Sequential execution on conventional processors can become a bottleneck when the dependency structure of the program contains subtasks that could be executed concurrently. This paper studies the Maximum Parallel Execution (MPE) problem for series-parallel task graphs under a staged batching model: compatible tasks inside one batch execute in parallel, while the selected batches are launched sequentially in a topological order that preserves precedence. We formulate MPE as a weighted clique-partitioning problem that minimizes the sum of batch execution times, with each batch cost determined by its slowest task. To solve this problem efficiently, we propose a Lagrangian-based Iterative Heuristic (LIH). LIH constructs a pricing-filtered restricted pool of feasible candidate batches from singleton columns and random greedy clique generation. It then applies Lagrangian pricing to guide column selection and uses a repair procedure to recover a legal clique partition. Experiments against a weighted mixed-graph-coloring branch-and-bound baseline and a randomized greedy baseline show that LIH matches the exact optimum in 91.25% of comparable instances, with an average gap of 0.073% and an average runtime of 18.19 ms. In the largest exact-reference node setting, the exact baseline requires hundreds of seconds on average, whereas LIH remains below 50 ms. We further present an end-to-end PLC ladder-logic case study in which PLCOpen-style programs are converted to MPE graphs, optimized by LIH, translated into FPGA-oriented HDL, and simulated against the original PLC scan execution.

Problem

• Maximum Parallel Execution
• Series-Parallel Task Graphs
• Safety-Critical Embedded Control
• Staged Batching Model
• Task Scheduling

Innovation

• Maximum Parallel Execution
• Series-Parallel Task Graphs
• Lagrangian-based Iterative Heuristic
• Clique Partitioning
• Safety-Critical Embedded Control