Scalable neuromorphic computing from autonomous spiking dynamics in a clockless reconfigurable chip

2026-05-15

AI Summary

This work proposes a clockless, asynchronous digital circuit-based spiking neural network architecture that overcomes the inherent trade-off between energy efficiency and reconfigurability in conventional digital neuromorphic systems. By leveraging continuous-time dynamics, the design implements Boolean spiking neurons with configurable excitatory and inhibitory synaptic weights, along with an efficient spike-encoding processing pipeline, on commercial off-the-shelf FPGAs. The approach establishes general-purpose asynchronous digital hardware as a viable neuromorphic platform, achieving analog-like computational efficiency without requiring specialized analog circuitry. Evaluated on audio classification tasks, the system demonstrates competitive accuracy while significantly reducing power consumption and accelerating processing speed, thereby validating its potential as an efficient and reconfigurable alternative for neuromorphic computing.

Abstract

We propose a scalable neuromorphic architecture based on spiking dynamics emerging from the autonomous time-continuous evolution of clockless (asynchronous) digital circuits. Implemented on commercially available field-programmable gate arrays (FPGAs), our system implements networks of interacting Boolean spiking neurons with configurable excitatory and inhibitory synaptic weights. A complete processing pipeline enables efficient handling of spike-encoded data for solving machine-learning tasks. We demonstrate competitive performance for an audio classification task with spike-based encoding and high-speed processing. Power consumption is significantly lower than traditional digital implementations; this makes our approach an efficient alternative that bridges the gap to dedicated analog neuromorphic systems without the need for specialized hardware design. More generally, our approach establishes clockless digital hardware as a viable platform for neuromorphic computing. It paves the way for reconfigurable chips to be turned into energy-efficient quasi-analog neuromorphic processors.

Problem

• neuromorphic computing
• clockless digital circuits
• spiking neurons
• reconfigurable chips
• energy efficiency

Innovation

• clockless neuromorphic computing
• spiking neural networks
• asynchronous digital circuits
• reconfigurable FPGA
• energy-efficient AI