LinkBo: An Adaptive Single-Wire, Low-Latency, and Fault-Tolerant Communications Interface for Variable-Distance Chip-to-Chip Systems

2025-09-01

AI Summary

To address the high latency, low throughput, and poor robustness of inter-chip single-wire communication, this paper proposes LinkBo—a novel adaptive low-latency single-wire interface. Methodologically, LinkBo integrates hardware interrupt-triggered transmission with protocol-level priority scheduling, enabling end-to-end delivery of high-priority messages within 50.4 μs—20× and 6.3× faster than 1-Wire and UNI/O, respectively. It further incorporates dynamic distance adaptation, hybrid-rate transmission, and a lightweight error-detection mechanism. Implemented on FPGA, the prototype achieves stable operation at 300 kbps over 15-m cables and up to 7.5 Mbps at 11 cm, significantly improving both spectral efficiency and noise resilience. Experimental results demonstrate substantial gains in real-time responsiveness, bandwidth scalability, and interference tolerance, making LinkBo well-suited for heterogeneous chip interconnects in diverse embedded and IoT scenarios.

Technology Category

• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Multiagent Systems: Agent Communication
• Machine Learning: Hardware-aware ML

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Energy management for devices in mobile Web and WoT environments
• Security and Privacy: Large-scale security measurements
• Responsible Web: Machine-in-the-loop, human agency and autonomy

Abstract

Cost-effective embedded systems necessitate utilizing the single-wire communication protocol for inter-chip communication, thanks to its reduced pin count in comparison to the multi-wire I2C or SPI protocols. However, current single-wire protocols suffer from increased latency, restricted throughput, and lack of robustness. This paper presents LinkBo, an innovative single-wire protocol that offers reduced latency, enhanced throughput, and greater robustness with hardware-interrupt for variable-distance inter-chip communication. The LinkBo protocol-level guarantees that high-priority messages are delivered with an error detection feature in just 50.4 $μ$s, surpassing current commercial options, 1-wire and UNI/O by at least 20X and 6.3X, respectively. In addition, we present the hardware architecture for this new protocol and its performance evaluation on a hardware platform consisting of two FPGAs. Our findings demonstrate that the protocol reliably supports wire lengths up to 15 meters with a data rate of 300 kbps, while reaching a maximum data rate of 7.5 Mbps over an 11 cm wire, providing reliable performance for varying inter-chip communication distances.

Problem

• Designing low-latency single-wire chip communication protocol
• Enhancing robustness for variable-distance inter-chip systems
• Improving throughput while maintaining fault tolerance

Innovation

• Adaptive single-wire protocol with hardware-interrupt
• Error detection with 50.4μs high-priority delivery
• Supports 15m wire length at 300kbps