SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics
🤖 AI Summary
To address the number-theoretic transform (NTT)—a critical computational bottleneck in fully homomorphic encryption (FHE)—this work proposes a hardware acceleration scheme based on superconducting single-flux-quantum (SFQ) technology. We design a deeply pipelined NTT-128 architecture integrating shift-register-based storage, ping-pong buffering, and multiphase clocking to enable scalable, large-scale NTT computation. The implementation leverages an RSFQ standard-cell library, Shoup’s modular multiplier, dual-coefficient FIFOs, and a precomputed twiddle-factor buffer to enhance energy efficiency and reliability. Experimental results demonstrate a throughput of 531 million NTTs per second at 34 GHz—over two orders of magnitude higher than state-of-the-art CMOS implementations. For a 2¹⁴-point NTT, latency is reduced to approximately 482 ns, achieving a critical-path throughput of 1.63 million operations per second. This represents the first SFQ-level hardware accelerator enabling ultra-high-speed, secure NTT computation for FHE.
Application Category
📝 Abstract
This research explores the use of superconductor electronics (SCE) for accelerating fully homomorphic encryption (FHE), focusing on the Number-Theoretic Transform (NTT), a key computational bottleneck in FHE schemes. We present SCE-NTT, a dedicated hardware accelerator based on superconductive single flux quantum (SFQ) logic and memory, targeting high performance and energy efficiency beyond the limits of conventional CMOS. To address SFQ constraints such as limited dense RAM and restricted fanin/fanout, we propose a deeply pipelined NTT-128 architecture using shift register memory (SRM). Designed for N=128 32-bit coefficients, NTT-128 comprises log2(N)=7 processing elements (PEs), each featuring a butterfly unit (BU), dual coefficient memories operating in ping-pong mode via FIFO-based SRM queues, and twiddle factor buffers. The BU integrates a Shoup modular multiplier optimized for a small area, leveraging precomputed twiddle factors. A new RSFQ cell library with over 50 parameterized cells, including compound logic units, was developed for implementation. Functional and timing correctness were validated using JoSIM analog simulations and Verilog models. A multiphase clocking scheme was employed to enhance robustness and reduce path-balancing overhead, improving circuit reliability. Fabricated results show the NTT-128 unit achieves 531 million NTT/sec at 34 GHz, over 100x faster than state-of-the-art CMOS equivalents. We also project that the architecture can scale to larger sizes, such as a 2^14-point NTT in approximately 482 ns. Key-switch throughput is estimated at 1.63 million operations/sec, significantly exceeding existing hardware. These results demonstrate the strong potential of SCE-based accelerators for scalable, energy-efficient secure computation in the post-quantum era, with further gains anticipated through advances in fabrication.
Problem
Research questions and friction points this paper is trying to address.
Accelerating Number-Theoretic Transform for fully homomorphic encryption
Overcoming hardware constraints of superconductor electronics
Achieving high performance and energy efficiency beyond CMOS limits
Innovation
Methods, ideas, or system contributions that make the work stand out.
Superconductor electronics accelerator for NTT
Deeply pipelined architecture with shift register memory
High-speed RSFQ cell library implementation
🔎 Similar Papers
No similar papers found.
