Next-Gen Interconnection Systems with Compute Express Link: a Comprehensive Survey

2024-12-28

AI Summary

To address the compute-memory co-design bottleneck imposed by the “memory wall,” this paper presents a systematic survey of CXL (Compute Express Link)-driven memory-centric interconnect architectures. We propose the first memory-semantics-based three-dimensional taxonomy—encompassing memory pooling, distributed shared memory, and unified memory—to clarify CXL 3.0’s technical pathways toward low latency, strong coherence, and scalability. By integrating address virtualization, MESIF cache coherence, coherent fabric protocols, and cross-node RDMA, our framework enables unified memory semantics across heterogeneous devices. Our analysis reveals CXL’s mechanistic roles in overcoming memory bandwidth limitations, cluster synchronization overhead, and heterogeneity-induced coordination barriers. The work establishes a theoretical foundation for next-generation interconnects and identifies open research directions toward high-bandwidth, low-latency, strongly coherent systems.

Technology Category

• Cognitive Modeling & Cognitive Systems: (Computational) Cognitive Architectures
• Machine Learning: Hardware-aware ML
• Search and Optimization: Distributed Search

Application Category

• Semantics and Knowledge: Data modeling to support human-machine intelligence, including LLMs agents, intelligent system behavior, explanations, and user-friendly interactions
• Systems and Infrastructure for Web, Mobile and WoT: Virtualization and resource management in Web systems and infrastructures
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs

Abstract

Interconnection is crucial for computing systems. However, the current interconnection performance between processors and devices, such as memory devices and accelerators, significantly lags behind their computing performance, severely limiting the overall performance. To address this challenge, Intel proposes Compute Express Link (CXL), an open industry-standard interconnection. With memory semantics, CXL offers low-latency, scalable, and coherent interconnection between processors and devices. This paper introduces recent advances in CXL-based interconnection systems with memory semantics. We classify the existing research into three categories: Pooling Memory, Distributed Shared Memory, and Unified Memory. Pooling Memory interconnects processors and memory, aims to address memory wall challenge. Distributed shared memory interconnects processors across nodes, aims to synchronize the cluster. Unified memory interconnects processors and accelerators, aims to enhance collaboration in heterogeneous computing systems. Finally, we discuss the future research and envision memory-centric computing with CXL.

Problem

• Interconnect Speed
• Memory Bottleneck
• System Efficiency

Innovation

• Compute Express Link (CXL)
• Memory-Centric Computing
• Enhanced Processor-Accelerator Collaboration