🤖 AI Summary
To address the need for multiple independent, programmable random sequences in cryptography, statistical simulation, and optimization computing, this work proposes a hardware-oriented programmable multi-sequence pseudo-random number generator (PRNG). The design, implemented in 65 nm CMOS, integrates linear feedback shift registers with configurable probabilistic mapping logic to enable, for the first time on a single chip, parallel generation of multiple statistically independent random sequences alongside real-time programmability of their statistical distributions. The chip occupies only 0.0013 mm² and consumes merely 0.57 pJ/bit. Post-layout simulations confirm negligible inter-sequence correlation, distribution modulation error ≤1.2%, and full compliance with the NIST SP 800-22 randomness test suite. This work achieves an unprecedented balance among high-quality randomness, minimal hardware overhead, and strong configurability, providing efficient hardware acceleration for non-uniformity-sensitive applications such as simulated annealing and CMOS-based Ising machines.
📝 Abstract
Pseudo-random number generators (PRNGs) are essential in a wide range of applications, from cryptography to statistical simulations and optimization algorithms. While uniform randomness is crucial for security-critical areas like cryptography, many domains, such as simulated annealing and CMOS-based Ising Machines, benefit from controlled or non-uniform randomness to enhance solution exploration and optimize performance. This paper presents a hardware PRNG that can simultaneously generate multiple uncorrelated sequences with programmable statistics tailored to specific application needs. Designed in 65nm process, the PRNG occupies an area of approximately 0.0013mm^2 and has an energy consumption of 0.57pJ/bit. Simulations confirm the PRNG's effectiveness in modulating the statistical distribution while demonstrating high-quality randomness properties.