AutoMCU: Feasibility-First MCU Neural Network Customization via LLM-based Multi-Agent Systems

2026-05-20

AI Summary

This work addresses the challenge of deploying neural networks on microcontroller units (MCUs), which is constrained by stringent memory, storage, and computational limitations. Existing approaches often rely on proxy metrics, incur high search costs, and fail to guarantee real-world deployability. To overcome these issues, the authors propose AutoMCU, a large language model–driven multi-agent system that generates network architectures directly from natural language task descriptions and hardware specifications. AutoMCU integrates vendor toolchains for hardware-in-the-loop validation, enabling early elimination of infeasible designs. Key innovations include hardware-aware architecture search, a state-isolated multi-agent scheduling mechanism, and a controlled evaluation protocol. Experiments demonstrate that AutoMCU achieves competitive accuracy on CIFAR-10/100, completes customization within 1–2 hours, substantially outperforms HW-NAS baselines requiring hundreds of GPU hours, and successfully validates deployments across multiple STM32 MCUs.

Abstract

Deploying neural networks on microcontroller units (MCUs) is critical for edge intelligence but remains challenging due to tight memory, storage, and computation constraints. Existing approaches, such as model compression and hardware-aware neural architecture search (HW-NAS), often depend on proxy metrics, incur high search cost, and do not fully bridge the gap between architecture design and verified deployment. This paper presents AutoMCU, a feasibility-first large language model (LLM)-based multi-agent system for automated neural network customization under MCU constraints. Given natural-language task requirements and hardware specifications, AutoMCU iteratively generates structured architecture candidates, filters infeasible designs through vendor toolchain feedback before training, evaluates feasible models under a controlled protocol, and verifies deployability through backend-grounded deployment analysis. AutoMCU includes two key mechanisms: 1) hardware-in-the-loop architecture generation for early elimination of undeployable candidates under RAM and Flash constraints, and 2) state-isolated multi-agent scheduling for stable coordination of proposal, training, evaluation, and deployment stages. Experiments on CIFAR-10 and CIFAR-100 under strict MCU constraints show that AutoMCU achieves competitive accuracy while reducing customization time to about 1--2 hours, compared with hundreds of GPU hours for representative MCU-oriented HW-NAS baselines. Comparisons with ColabNAS and the LLM-based NAS method GENIUS on NAS-Bench-201 further demonstrate the effectiveness and stability of AutoMCU. Real-device deployments on multiple STM32 microcontrollers validate its practical applicability to MCU-scale edge intelligence.

Problem

• MCU
• neural network deployment
• hardware constraints
• feasibility
• edge intelligence

Innovation

• LLM-based multi-agent system
• hardware-in-the-loop
• feasibility-first NAS
• MCU deployment
• automated neural architecture customization