FQTree: Fine-grained Quantization and Hardware Generation of Boosted Decision Trees

2026-08-12

AI Summary

This work addresses the high hardware overhead and accuracy degradation in existing decision tree deployments caused by uniform or manual fixed-point quantization. To overcome these limitations, the authors propose FQTree, a novel quantization algorithm, and QXGB, an accompanying framework. Their approach introduces a leaf-node quantization scheme that combines a global quantization step size with tree-level offsets, enabling compact non-negative integer representations, controllable clipping/pruning, and bias folding. Quantization error is dynamically compensated during the boosting process. Integrated with fine-grained quantization-aware training and a compiler-driven automatic hardware generation pipeline, the method achieves 26%–57% reduction in LUT usage on FPGA compared to state-of-the-art baselines across the JSC, MNIST, and NID datasets, while maintaining or even improving model accuracy.

Abstract

Boosted decision trees (BDTs) are widely used in latency-critical applications, but efficient hardware deployment remains challenging. Existing designs often rely on uniform or manually tuned fixed-point formats, which can introduce unnecessary hardware cost or accuracy loss. This work presents the FQTree algorithm{https://github.com/ecs-bristol/FQTree} for fine-grained quantization-aware training of BDTs, together with the QXGB framework for automatic hardware generation. FQTree introduces a hardware-oriented leaf-value quantization scheme that uses a global quantization step together with a tree-wise shift, enabling compact non-negative integer leaf representations, controlled clipping/pruning, and bias folding to reduce datapath cost. This work further applies this quantization during boosting so that later trees adapt to the errors of the already-quantized ensemble, and then lowers the trained model into low-latency hardware implementations through a compiler-based flow. Results on JSC, MNIST, and NID show that our method reduces LUT usage by 26-57\% compared with the state-of-the-art FPGA-based BDT designs while matching or improving accuracy.

Problem

• Boosted Decision Trees
• Hardware Deployment
• Quantization
• Fixed-point Formats
• Latency-critical Applications

Innovation

• fine-grained quantization
• boosted decision trees
• hardware-aware training
• quantization-aware boosting
• FPGA acceleration