DR-CircuitGNN: Training Acceleration of Heterogeneous Circuit Graph Neural Network on GPUs

2025-08-22

AI Summary

To address the low training efficiency of Heterogeneous Graph Neural Networks (HGNNs) on large-scale, heterogeneous circuit graphs in EDA, this paper proposes a GPU-accelerated framework. The method innovatively integrates a row-wise sparse-aware Dynamic-ReLU mechanism into HGNNs and synergistically combines parallelized multi-stream CPU-GPU cooperative scheduling, optimized sparse matrix multiplication, multithreaded subgraph partitioning, and GPU kernel-level tuning. This design overcomes the computational bottleneck of conventional serial message passing, substantially improving throughput. On the CircuitNet benchmark suite, the framework achieves 3.51× and 4.09× speedups for forward and backward propagation, respectively—2.71× faster than the official DGL implementation—with negligible accuracy degradation. The core contribution lies in the first deep coupling of sparse-aware Dynamic-ReLU with heterogeneous graph computation, enabling both high efficiency and high fidelity in circuit-level GNN training acceleration.

Technology Category

• Machine Learning: Hardware-aware ML
• Constraint Satisfaction and Optimization: Distributed CSP/Optimization
• Computer Vision: Learning & Optimization for CV

Application Category

• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines

Abstract

The increasing scale and complexity of integrated circuit design have led to increased challenges in Electronic Design Automation (EDA). Graph Neural Networks (GNNs) have emerged as a promising approach to assist EDA design as circuits can be naturally represented as graphs. While GNNs offer a foundation for circuit analysis, they often fail to capture the full complexity of EDA designs. Heterogeneous Graph Neural Networks (HGNNs) can better interpret EDA circuit graphs as they capture both topological relationships and geometric features. However, the improved representation capability comes at the cost of even higher computational complexity and processing cost due to their serial module-wise message-passing scheme, creating a significant performance bottleneck. In this paper, we propose DR-CircuitGNN, a fast GPU kernel design by leveraging row-wise sparsity-aware Dynamic-ReLU and optimizing SpMM kernels during heterogeneous message-passing to accelerate HGNNs training on EDA-related circuit graph datasets. To further enhance performance, we propose a parallel optimization strategy that maximizes CPU-GPU concurrency by concurrently processing independent subgraphs using multi-threaded CPU initialization and GPU kernel execution via multiple cudaStreams. Our experiments show that on three representative CircuitNet designs (small, medium, large), the proposed method can achieve up to 3.51x and 4.09x speedup compared to the SOTA for forward and backward propagation, respectively. On full-size CircuitNet and sampled Mini-CircuitNet, our parallel design enables up to 2.71x speed up over the official DGL implementation cuSPARSE with negligible impact on correlation scores and error rates.

Problem

• Accelerating training of heterogeneous GNNs for circuit analysis
• Overcoming computational bottlenecks in EDA graph processing
• Optimizing GPU performance for sparse message-passing operations

Innovation

• Leveraging row-wise sparsity-aware Dynamic-ReLU
• Optimizing SpMM kernels during message-passing
• Parallel CPU-GPU concurrency with multi-threaded processing