🤖 AI Summary
To address the low computational density, high error rates, and large latency of SRAM-based compute-in-memory (CIM) macros in complex multiply-accumulate (MAC) operations under the 28 nm process, this work proposes a hybrid digital/analog CIM architecture. It synergistically combines high-bit digital CIM with low-bit analog CIM and employs a two-dimensional weighted capacitor array to directly output complex real and imaginary components within a single cycle—eliminating the need for input digital-to-analog converters (DACs). This design circumvents the precision limitations of conventional analog CIM and the area overhead of fully digital CIM. Implemented in a 28 nm 6T-SRAM technology, the macro achieves an ultra-high memory density of 1.80 Mb/mm² and a low root-mean-square error of 0.435%. The architecture significantly improves energy efficiency and computational throughput for complex arithmetic, establishing a high-density, high-accuracy CIM hardware foundation for spectrally efficient wireless communications and AI acceleration.
📝 Abstract
A 28nm dense 6T-SRAM Digital(D)/Analog(A) Hybrid compute-in-memory (CIM) macro supporting complex num-ber MAC operation is presented. By introducing a 2D-weighted Capacitor Array, a hybrid configuration is adopted where digital CIM is applied only to the upper bits and ana-log CIM is applied to the rest, without the need for input DACs resulting in improved accuracy and lower area overhead. The CIM prototype macro achieves 1.80 Mb/mm2 memory density and 0.435% RMS error. Complex CIM unit outputs real and imaginary part with a single conversion to reduce latency.