SOT-MRAM Bitcell Scaling with BEOL Read Selectors: A DTCO Study

2025-08-25

AI Summary

In heterogeneous systems, spin-orbit torque magnetic random-access memory (SOT-MRAM) faces a bit-cell area scaling bottleneck when deployed as a last-level cache (LLC), primarily due to routing congestion from the 2T1R magnetic tunnel junction (MTJ) structure. Method: This work proposes a novel bit-cell architecture integrating back-end-of-line (BEOL) read selectors—either IGZO-FETs or diodes—combined with design-technology co-optimization (DTCO), including enhanced fin utilization for write transistors and low-resistance bitline design. Contribution/Results: At the 7 nm node, the approach achieves 10–40% area reduction, attaining bit-cell density comparable to sub-N3 SRAM. Write current and data retention (0.1–100 s) meet cache requirements. However, read latency increases by 3–5 ns, and the diode-based variant suffers a 2.5–5× energy-efficiency degradation, highlighting critical PPA (power, performance, area) trade-offs inherent in BEOL selector integration.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Evaluation and Analysis
• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Energy management for devices in mobile Web and WoT environments
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics
• Security and Privacy: Large-scale security measurements

Abstract

This work explores the cross-node scaling potential of SOT-MRAM for last-level caches (LLCs) under heterogeneous system scaling paradigm. We perform extensive Design-Technology Co-Optimization (DTCO) exercises to evaluate the bitcell footprint for different cell configurations at a representative 7 nm technology and to assess their implications on read and write power-performance. We crucially identify the MTJ routing struggle in conventional two-transistor one-resistor (2T1R) SOT-MRAMs as the primary bitcell area scaling challenge and propose to use BEOL read selectors (BEOL RSs) that enable (10 -- 40) % bitcell area reduction and eventually match sub-N3 SRAM. On writability, we affirm that BEOL RS-based bitcells could meet the required SOT switching current, provided the magnetic free layer properties be engineered in line with LLC-specific, (0.1 -- 100) s retention targets. This is particularly to attribute to their (i) more available Si fins for write transistor and (ii) lower bitline resistance at reduced cell width. We nevertheless underscore the read tradeoff associated with BEOL RSs, with the low-drive IGZO-FET selector sacrificing the latency up to (3 -- 5) ns and the imperfectly rectifying diode selectors suffering (2.5 -- 5)$ imes$ energy cost relative to 2T1R. This article thus highlights the realistic prospects and hurdles of BEOL RSs towards holistic power-performance-area scaling of SOT-MRAM.

Problem

• Scaling SOT-MRAM bitcell area for last-level caches
• Addressing MTJ routing challenges in 2T1R configurations
• Evaluating read-write tradeoffs with BEOL selectors

Innovation

• BEOL read selectors reduce bitcell area
• BEOL RSs meet SOT switching current requirements
• BEOL RSs introduce read latency and energy tradeoffs