Visualising CTL Witnesses and Counterexamples -- Extended Version

πŸ“… 2026-04-22
πŸ“ˆ Citations: 0
✨ Influential: 0
πŸ“„ PDF
πŸ€– AI Summary
This work addresses the limited interpretability of Computation Tree Logic (CTL) model checking results, which stems from the absence of intuitive, visualizable evidence formsβ€”CTL counterexamples being notably harder to comprehend than Linear Temporal Logic (LTL) traces. The paper proposes a unified evidence framework for CTL over explicit-state models, capable of representing both witnesses for satisfied properties and counterexamples for violations. Minimal evidence structures are formally defined for each temporal operator, and a human-centric visualization scheme is developed by integrating formal reasoning with graphical techniques. A complete toolchain implementing this approach is presented. All theoretical claims are rigorously proven, significantly enhancing the readability and explainability of CTL model checking outcomes.

Technology Category

Application Category

πŸ“ Abstract
One of the advantages of LTL over CTL is that the notion of a counterexample is easy to grasp, visualise and process: it is a trace that violates the property at hand. In this paper we propose a notion of evidence for CTL properties on explicit-state models -- which equally serves as witness for satisfied properties and counterexample for violated ones -- and how to visualise it, with the main aim of (human) comprehension. The main contribution consists of a formal model of evidence, a characterisation of minimal evidence per temporal operator, and a concrete, implemented proposal for its visualisation. This is the extended version of a paper published in SPIN 2026, containing the proofs of all results.
Problem

Research questions and friction points this paper is trying to address.

CTL
counterexample
witness
visualization
explicit-state models
Innovation

Methods, ideas, or system contributions that make the work stand out.

CTL evidence
counterexample visualization
witness generation
temporal logic verification
explicit-state model
πŸ”Ž Similar Papers
No similar papers found.