ListenToJESD204B: A Lightweight Open-Source JESD204B IP Core for FPGA-Based Ultrasound Acquisition systems

2025-08-20

AI Summary

To address the stringent requirements of ultrasound systems—namely, high channel count (hundreds), high sampling rates (≥80 MSPS), and Subclass 1 deterministic synchronization—conventional LVDS interfaces are constrained by bandwidth limitations, excessive pin count, and non-deterministic latency. This paper proposes a lightweight, open-source JESD204B receiver IP core targeting Xilinx Zynq UltraScale+ FPGAs, implemented in synthesizable SystemVerilog. The design consumes only 107 CLBs—79% fewer logic resources than commercial alternatives. It supports quad-lane 12.8 Gb/s reception via GTH/GTY transceivers, SYSREF-locked LMFC generation, LFSR-based descrambling, and elastic buffering, ensuring full protocol compliance and Subclass 1 deterministic latency. Hardware validation demonstrates zero bit errors over 30 minutes of continuous transmission at 12.8 Gb/s per link, delivering 80 MSPS/16-bit data. The IP is fully compatible with the AFE58JD48 ADC and interoperable with JESD204C ecosystems.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Data management and stream processing for Web, mobile and wireless applications
• User Modeling, Personalization and Recommendation: On-Device user modeling, personalization, and recommendation
• Security and Privacy: Large-scale security measurements

Abstract

The demand for hundreds of tightly synchronized channels operating at tens of MSPS in ultrasound systems exceeds conventional low-voltage differential signaling links' bandwidth, pin count, and latency. Although the JESD204B serial interface mitigates these limitations, commercial FPGA IP cores are proprietary, costly, and resource-intensive. We present ListenToJESD204B, an open-source receiver IP core released under a permissive Solderpad 0.51 license for AMD Xilinx Zynq UltraScale+ devices. Written in synthesizable SystemVerilog, the core supports four GTH/GTY lanes at 12.8 Gb/s and provides cycle-accurate AXI-Stream data alongside deterministic Subclass~1 latency. It occupies only 107 configurable logic blocks (approximately 437 LUTs), representing a 79% reduction compared to comparable commercially available IP. A modular data path featuring per-lane elastic buffers, SYSREF-locked LMFC generation, and optional LFSR descrambling facilitates scaling to high lane counts. We verified protocol compliance through simulation against the Xilinx JESD204C IP in JESD204B mode and on hardware using TI AFE58JD48 ADCs. Block stability was verified by streaming 80 MSPS, 16-bit samples over two 12.8 Gb/s links for 30 minutes with no errors.

Problem

• Overcoming bandwidth and latency limitations in ultrasound data acquisition
• Providing an open-source alternative to proprietary JESD204B FPGA IP cores
• Enabling high-speed synchronized multi-channel ultrasound systems

Innovation

• Open-source JESD204B IP core for FPGAs
• Supports four 12.8 Gb/s lanes with AXI-Stream
• Uses modular design with elastic buffers