Tight Inter-Core Cache Contention Analysis for WCET Estimation on Multicore Systems

2025-08-19

AI Summary

In multicore systems, inter-core cache contention in shared caches leads to significant overestimation of worst-case execution time (WCET), primarily because existing methods rely solely on coarse partial ordering of program regions to identify contention, neglecting actual cache state and memory access frequencies. This paper proposes a tighter WCET analysis method: first, identifying critical memory references affected by remote-core accesses based on program region ordering; second, constructing a fine-grained cache contention model that integrates precise local and remote memory block access counts; and third, computing the maximum number of cache misses under worst-case scenarios via dynamic programming. Experimental evaluation shows an average reduction of 52.31% in inter-core cache interference and 8.94% in WCET estimates, with manageable computational overhead. The key innovation lies in incorporating access-frequency–aware modeling and dynamic programming optimization into WCET analysis, substantially improving estimation accuracy.

Technology Category

• Constraint Satisfaction and Optimization: Distributed CSP/Optimization
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Cognitive Modeling & Cognitive Systems: Analogy

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Security and Privacy: Large-scale security measurements
• Web Mining and Content Analysis: Web measurements

Abstract

WCET (Worst-Case Execution Time) estimation on multicore architecture is particularly challenging mainly due to the complex accesses over cache shared by multiple cores. Existing analysis identifies possible contentions between parallel tasks by leveraging the partial order of the tasks or their program regions. Unfortunately, they overestimate the number of cache misses caused by a remote block access without considering the actual cache state and the number of accesses. This paper reports a new analysis for inter-core cache contention. Based on the order of program regions in a task, we first identify memory references that could be affected if a remote access occurs in a region. Afterwards, a fine-grained contention analysis is constructed that computes the number of cache misses based on the access quantity of local and remote blocks. We demonstrate that the overall inter-core cache interference of a task can be obtained via dynamic programming. Experiments show that compared to existing methods, the proposed analysis reduces inter-core cache interference and WCET estimations by 52.31% and 8.94% on average, without significantly increasing computation overhead.

Problem

• Analyzing inter-core cache contention for accurate WCET estimation
• Reducing overestimation of cache misses in multicore systems
• Quantifying cache interference through fine-grained access analysis

Innovation

• Fine-grained cache contention analysis considering access quantity
• Dynamic programming to compute inter-core cache interference
• Reduces cache interference and WCET estimation significantly