π€ AI Summary
As technology scales down and supply voltages decrease, soft error probability (SEP) in nanoscale circuits is increasingly affected by the coupled effects of process variation (PV) and agingβyet existing methods either neglect this coupling or rely on computationally expensive Monte Carlo simulations, hindering scalability for large-scale reliability optimization. This paper proposes the first analytical framework jointly modeling PV and aging, introducing an enhanced electrical masking model integrated with a statistical SEP computation methodology. Leveraging theoretical derivation validated by Monte Carlo simulation, the approach achieves high accuracy while significantly improving computational efficiency. Experimental results demonstrate a ~2.5% reduction in computational overhead compared to conventional Monte Carlo simulation, without sacrificing estimation accuracy. The framework thus provides an efficient, scalable foundation for reliability-driven design of large digital circuits.
π Abstract
As technology scales, nano-scale digital circuits face heightened susceptibility to single event upsets (SEUs) and transients (SETs) due to shrinking feature sizes and reduced operating voltages. While logical, electrical, and timing masking effects influence soft error probability (SEP), the combined impact of process variation (PV) and aging-induced degradation further complicates SEP estimation. Existing approaches often address PV or aging in isolation, or rely on computationally intensive methods like Monte Carlo simulations, limiting their practicality for large-scale circuit optimization. This paper introduces a novel framework for SEP analysis that holistically integrates PV and aging effects. We propose an enhanced electrical masking model and a statistical methodology to quantify soft error probability under process and aging variations. Experimental results demonstrate that the proposed approach achieves high accuracy while reducing computational overhead by approximately 2.5% compared to Monte Carlo-based methods. This work advances the design of reliable nano-scale circuits by enabling efficient, accurate SEP estimation in the presence of manufacturing variability and long-term transistor degradation.