IzhiRISC-V -- a RISC-V-based Processor with Custom ISA Extension for Spiking Neuron Networks Processing with Izhikevich Neurons

2025-08-18

AI Summary

To address the low instruction efficiency and limited energy-efficiency gains of executing the Izhikevich spiking neuron model on general-purpose RISC-V processors, this paper proposes a neuromorphic-computing-oriented RISC-V instruction set architecture (ISA) extension. It introduces, for the first time in RISC-V, dedicated neuromorphic instructions for Izhikevich model state updates and designs a custom arithmetic logic unit (ALU) to enable parallel computation and single-cycle update of multiple neuronal state variables. The architecture preserves full backward compatibility with base RISC-V while requiring only lightweight ISA extensions and a specialized data path. This reduces the instruction count per neuron update—cutting CPI by up to 42%—and significantly lowers energy consumption. Experimental results demonstrate a 3.1× improvement in neuronal throughput over standard RISC-V implementations under identical process technology, establishing a new paradigm for energy-efficient, scalable brain-inspired computing hardware.

Technology Category

• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Machine Learning: Hardware-aware ML
• Computer Vision: Learning & Optimization for CV

Application Category

• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs

Abstract

Spiking Neural Network processing promises to provide high energy efficiency due to the sparsity of the spiking events. However, when realized on general-purpose hardware -- such as a RISC-V processor -- this promise can be undermined and overshadowed by the inefficient code, stemming from repeated usage of basic instructions for updating all the neurons in the network. One of the possible solutions to this issue is the introduction of a custom ISA extension with neuromorphic instructions for spiking neuron updating, and realizing those instructions in bespoke hardware expansion to the existing ALU. In this paper, we present the first step towards realizing a large-scale system based on the RISC-V-compliant processor called IzhiRISC-V, supporting the custom neuromorphic ISA extension.

Problem

• Enhance energy efficiency in Spiking Neural Network processing
• Address inefficiency of general-purpose hardware like RISC-V
• Introduce custom ISA extension for neuromorphic instructions

Innovation

• Custom ISA extension for spiking neurons
• Bespoke hardware expansion to ALU
• RISC-V processor with neuromorphic instructions