ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package

2024-10-21

arXiv.org

AI Summary

To address real-time and energy-efficiency challenges in chiplet co-control for 2.5D system-in-package (SiP) integration, this work designs and tape-outs Kairos—an open-source, low-power, real-time multicore RISC-V controller. Kairos introduces the first AXI4-compliant die-to-die (D2D) interconnect link supporting 2.5D heterogeneous integration. It integrates a CV32RT real-time core, a custom DMA engine, and a tightly coupled programmable multicore accelerator to enable periodic sensor data acquisition and low-overhead inter-chip communication. Fabricated in TSMC 65 nm CMOS, Kairos executes model-predictive control at 290 MHz with only 30 mW power consumption. Its D2D link incurs just 2.9% area overhead per channel, achieves 1.3 pJ/bit energy efficiency, and delivers a peak duplex bandwidth of 51 Gb/s—significantly mitigating inter-chip communication bottlenecks in 2.5D SiP systems.

Technology Category

• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Intelligent Robots: Multimodal Perception & Sensor Fusion
• Constraint Satisfaction and Optimization: Distributed CSP/Optimization

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Data management and stream processing for Web, mobile and wireless applications
• Search and Retrieval-Augmented AI: Vertical and domain-specific search
• Responsible Web: Data and user privacy-enhancing technologies for the Web

Abstract

The increasing complexity of real-time control algorithms and the trend toward 2.5D technology necessitate the development of scalable controllers for managing the complex, integrated operation of chiplets within 2.5D systems-in-package. These controllers must provide real-time computing capabilities and have chiplet-compatible IO interfaces for communication with the controlled components. This work introduces ControlPULPlet, a chiplet-compatible, real-time multi-core RISC-V controller, which is available as an open-source release. It includes a 32-bit CV32RT core for efficient interrupt handling and a specialized direct memory access (DMA) engine to automate periodic sensor readouts. A tightly-coupled programmable multi-core accelerator is integrated via a dedicated AXI4 port. A flexible AXI4-compatible die-to-die (D2D) link supports inter-chiplet communication in 2.5D systems and enables high-bandwidth transfers in traditional 2D monolithic setups. We designed and fabricated ControlPULPlet as a silicon prototype called Kairos using TSMC's 65nm CMOS technology. Kairos executes predictive control algorithms at up to 290 MHz while consuming just 30 mW of power. The D2D link requires only 16.5 kGE in physical area per channel, adding just 2.9% to the total system area. It supports off-die access with an energy efficiency of 1.3 pJ/b and achieves a peak duplex transfer rate of 51 Gb/s per second at 200 MHz.

Problem

• Scalable controllers for 2.5D SiP real-time control
• Minimizing die-to-die communication performance penalty
• Open-source RISC-V controller for SiP integration

Innovation

• Multi-core RISC-V controller for SiP integration
• Specialized DMA engine for sensor readout
• AXI4-compatible die-to-die link for 2.5D SiPs