High-Performance NTT Accelerators for PQC leveraging Unified Redundant Arithmetic and Fine-Tuned Microarchitecture

2026-07-01

AI Summary

This work addresses efficiency bottlenecks in existing NTT hardware accelerators—particularly in modular reduction, correction steps, inverse transform scaling, and FPGA implementation—that hinder lattice-based cryptographic performance. The authors propose a parallel iterative NTT/INTT accelerator based on unified redundant arithmetic, which eliminates conditional corrections in Montgomery modular multiplication through a novel redundant number representation. The inverse transform scaling is seamlessly integrated into a general-purpose arithmetic unit, and a hierarchical Montgomery multiplier is designed to efficiently map onto FPGA DSP resources. Experimental results demonstrate that the proposed architecture achieves significantly higher clock frequencies and reduced execution time, outperforming state-of-the-art designs in both resource utilization and throughput efficiency, thereby accelerating NTT computations in post-quantum cryptography.

Abstract

Post-quantum cryptography and privacy-preserving technologies are expected to play a central role in future secure communication systems. Lattice-based PQC schemes such as ML-KEM (CRYSTALS-Kyber) and ML-DSA (CRYSTALS-Dilithium) rely heavily on large-degree polynomial arithmetic, making the Number Theoretic Transform (NTT) a key computational primitive. Although existing hardware accelerators exploit parallelism and pipelining to support both NTT and INTT, their efficiency is often limited by the overhead of modular reduction and correction steps, inverse-transform scaling operations, and suboptimal FPGA implementations. This work addresses these limitations by proposing parallel iterative NTT/INTT accelerators based on optimized unified butterfly units. We introduce a novel redundant number representation that eliminates conditional corrections for both Montgomery modulo multiplication and combined subtract-multiply operations, and integrate inverse-transform scaling into existing arithmetic hardware to avoid dedicated scaling units. Furthermore, we design hierarchical Montgomery multipliers that map efficiently onto FPGA DSP resources, reducing hardware cost while enabling high operating frequencies. FPGA-based experimental results demonstrate higher clock frequencies, reduced execution times, and competitive resource utilization, supporting efficient NTT acceleration for PQC and related privacy-preserving applications.

Problem

• NTT accelerator
• post-quantum cryptography
• modular reduction
• FPGA implementation
• polynomial arithmetic

Innovation

• Number Theoretic Transform
• Unified Redundant Arithmetic
• Montgomery Multiplier
• FPGA Acceleration
• Post-Quantum Cryptography