Real-time CARFAC Cochlea Model Acceleration on FPGA for Underwater Acoustic Sensing Systems

2025-08-10

AI Summary

To address the real-time performance and energy-efficiency bottlenecks of the CARFAC cochlear model in underwater acoustic sensing, this work proposes a software-hardware co-design acceleration framework on the AMD Kria KV260 platform. The approach employs Rust for a low-overhead control layer and leverages FPGA acceleration with time-division multiplexing, deep pipelining, and a division-free CARFAC core implementation. The system achieves real-time, synchronized preprocessing for up to 64 hydrophones at 256 kHz sampling rate. It consumes only 13.5% of the FPGA’s logic resources and operates at just 3.11 W total board power, while preserving biological fidelity. This is the first demonstration of full-rate, high-channel-count CARFAC deployment on an embedded FPGA platform. The architecture delivers significantly improved throughput and energy efficiency, establishing a scalable foundation for edge-intelligent, biomimetic underwater auditory processing.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Intelligent Robots: Multimodal Perception & Sensor Fusion

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Data management and stream processing for Web, mobile and wireless applications
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• User Modeling, Personalization and Recommendation: On-Device user modeling, personalization, and recommendation

Abstract

This paper presents a real-time, energy-efficient embedded system implementing an array of Cascade of Asymmetric Resonators with Fast-Acting Compression (CARFAC) cochlea models for underwater sound analysis. Built on the AMD Kria KV260 System-on-Module (SoM), the system integrates a Rust-based software framework on the processor for real-time interfacing and synchronization with multiple hydrophone inputs, and a hardware-accelerated implementation of the CARFAC models on a Field-Programmable Gate Array (FPGA) for real-time sound pre-processing. Compared to prior work, the CARFAC accelerator achieves improved scalability and processing speed while reducing resource usage through optimized time-multiplexing, pipelined design, and elimination of costly division circuits. Experimental results demonstrate 13.5% hardware utilization for a single 64-channel CARFAC instance and a whole board power consumption of 3.11 W when processing a 256 kHz input signal in real time.

Problem

• Real-time underwater sound analysis using CARFAC models
• Energy-efficient FPGA acceleration for cochlea model processing
• Scalable hardware design reducing resource usage and power

Innovation

• FPGA-accelerated CARFAC cochlea model
• Rust-based real-time software framework
• Optimized time-multiplexing and pipelined design