🤖 AI Summary
To address the co-design challenge of ultra-low latency and high bandwidth in experimental data stream transmission within edge computing clusters, this paper proposes an FPGA-based end-to-end acceleration architecture. The architecture innovatively integrates hardware-accelerated streaming compression/decompression, fine-grained data sharding and reassembly, UDP packet-level NAT redirection, and high-speed forwarding—enabling seamless, low-overhead integration from edge nodes to compute clusters. Compared to conventional TCP/IP stack implementations, it reduces end-to-end transmission latency by 42% (measured) and achieves >92% bandwidth utilization. Its compatibility with and scalability on U.S. Department of Energy (DOE) scientific infrastructure are validated through cross-domain experiments across JLab–ESnet–LBNL. This work establishes a deployable hardware acceleration paradigm for time-sensitive scientific data processing.
📝 Abstract
Thomas Jefferson National Accelerator Facility (JLab) has partnered with Energy Sciences Network (ESnet) to define and implement an edge to compute cluster computational load balancing acceleration architecture. The ESnet-JLab FPGA Accelerated Transport (EJFAT) architecture focuses on FPGA acceleration to address compression, fragmentation, UDP packet destination redirection (Network Address Translation (NAT)) and decompression and reassembly.
EJFAT seamlessly integrates edge and cluster computing to support direct processing of streamed experimental data. This will directly benefit the JLab science program as well as data centers of the future that require high throughput and low latency for both time-critical data acquisition systems and data center workflows.
The EJFAT project will be presented along with how it is synergistic with other DOE activities such as an Integrated Research Infrastructure (IRI), and recent results using data sources at JLab, an EJFAT LB at ESnet, and computational cluster resources at Lawrence Berkeley National Laboratory (LBNL).