NeuroRing: Scaling Spiking Neural Networks via Multi-FPGA Bidirectional Ring Topologies and Stream-Dataflow Architectures

2026-04-30

AI Summary

This work addresses the challenges of executing large-scale spiking neural networks (SNNs), which are often constrained by sparse spike communication and synchronization overhead, with existing hardware struggling to balance programmability, energy efficiency, and scalability. The paper proposes NeuroRing, a modular SNN accelerator that uniquely integrates a streaming dataflow architecture with a bidirectional ring topology—combining these two paradigms for the first time in SNN acceleration. Implemented on FPGA via high-level synthesis (HLS), NeuroRing supports both single- and multi-FPGA deployments and enables seamless integration with the NEST simulator. Evaluated on a cortical microcircuit benchmark, NeuroRing achieves a real-time factor of 0.83 while accurately reproducing key spiking activity statistics from NEST, demonstrating strong and weak scaling capabilities alongside high energy efficiency.

Abstract

Spiking neural networks (SNNs) are a promising paradigm for energy-efficient event-driven computation, but large-scale SNN execution remains challenging because sparse spike communication and synchronization can dominate runtime. Existing solutions across CPU, GPU, ASIC, and FPGA platforms offer different trade-offs between programmability, efficiency, and scalability. To address this gap, we present NeuroRing, a modular and scalable SNN accelerator based on a stream-dataflow architecture and a bidirectional ring topology, implemented in High-Level Synthesis (HLS) on programmable FPGAs. NeuroRing supports modular single- and multi-FPGA deployment and is compatible with existing SNN workflows through integration with the NEST simulator. We evaluate NeuroRing on the cortical microcircuit benchmark and a Sudoku constraint-satisfaction workload. Results show that NeuroRing preserves the key activity statistics of the NEST reference model, achieves faster-than-real-time execution of the full-scale cortical microcircuit with a real-time factor (RTF) of 0.83, exhibits meaningful strong and weak scaling, and provides competitive energy efficiency on two programmable FPGAs. These results position NeuroRing as a flexible and scalable platform for both neuroscience simulation and broader event-driven applications.

Problem

• Spiking Neural Networks
• Scalability
• Sparse Communication
• Synchronization
• Energy Efficiency

Innovation

• Spiking Neural Networks
• Stream-Dataflow Architecture
• Bidirectional Ring Topology
• Multi-FPGA Acceleration
• High-Level Synthesis